JPS63151069A - Semiconductive memory device - Google Patents
Semiconductive memory deviceInfo
- Publication number
- JPS63151069A JPS63151069A JP61299413A JP29941386A JPS63151069A JP S63151069 A JPS63151069 A JP S63151069A JP 61299413 A JP61299413 A JP 61299413A JP 29941386 A JP29941386 A JP 29941386A JP S63151069 A JPS63151069 A JP S63151069A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- column shaped
- shaped electrodes
- electrodes
- diffusion layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010408 film Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 239000010409 thin film Substances 0.000 claims abstract description 4
- 239000004020 conductor Substances 0.000 claims abstract description 3
- 238000009792 diffusion process Methods 0.000 claims description 15
- 238000000034 method Methods 0.000 abstract description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract description 5
- 239000010931 gold Substances 0.000 abstract description 5
- 229910052737 gold Inorganic materials 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 3
- 229920005591 polysilicon Polymers 0.000 abstract description 3
- 239000013078 crystal Substances 0.000 abstract description 2
- 238000001704 evaporation Methods 0.000 abstract 1
- 239000003990 capacitor Substances 0.000 description 9
- 230000010354 integration Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は一時的にコンデンサに電荷を貯えることによっ
て信号を記憶する機能を有する半導体記憶装置に関する
ものである。本装置はコンピュータに用いられプログラ
ムやデータを記憶させるために使用される。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device having a function of storing signals by temporarily storing charge in a capacitor. This device is used in a computer to store programs and data.
従来の技術
半導体記憶装置の集積度は約３年毎に４倍に増大してき
ている。集積度の向上は記憶単位であるメモリーセルの
面積縮小によりもたらされてきた。BACKGROUND OF THE INVENTION The degree of integration of conventional semiconductor memory devices has quadrupled approximately every three years. Improvements in the degree of integration have been brought about by reducing the area of memory cells, which are storage units.
しかしメモリーセルの面積縮小は必然的に記憶のための
静電容量の減少をもたらし、それにより読出し信号の低
下やリフトエラー率の増大が引起こされる。それを避け
るため、半導体基板に数μｍの深さの溝を堀りその側面
をキャパシターとして利用することが提案されている。However, a reduction in the area of a memory cell inevitably results in a reduction in storage capacitance, which causes a reduction in read signal and an increase in lift error rate. In order to avoid this, it has been proposed to dig a groove several micrometers deep in the semiconductor substrate and use the side surface of the groove as a capacitor.
セル寸法をＬＸＷ、溝深さをＨとすると、セル面積に対
する溝側面の比γは次式で表わされる。When the cell dimensions are LXW and the groove depth is H, the ratio γ of the groove side surface to the cell area is expressed by the following equation.
ｒ＝２ＨＸ（Ｌ＋Ｗ）／（Ｌ−Ｗ）
Ｌ＝３Ｗの関係が保たれるとすると
８ Ｈ
ｒ ＝ （−） ｘ （７−）
となる。例えば！＝１μＩＩＩＸＨ＝４μｍのとき
′γ＝１０．７、溝をもっと深くすればｒは増えていく
が、微細加工は困難である。r=2HX(L+W)/(L-W) If the relationship L=3W is maintained, then 8 H r = (-) x (7-). for example! When = 1μIIIXH = 4μm
'γ = 10.7. If the groove is made deeper, r will increase, but microfabrication is difficult.
発明が解決しようとする問題点
従って溝側面を利用する方法でもキャパシターの電極面
積を１０倍以上にするのは難しく、他方誘電体の誘電率
を大きくする試みもあるが、その場合誘電体薄膜のリー
ク電も大きくなるなどの問題がある。Problems to be Solved by the Invention Therefore, it is difficult to increase the electrode area of a capacitor by more than 10 times even by using the groove side surface.On the other hand, there are attempts to increase the dielectric constant of the dielectric material, but in that case, it is difficult to increase the electrode area of the capacitor by more than 10 times. There are also problems such as increased leakage current.
本発明は以上の様な高集積化によるメモリセル容量の減
少という問題点を解決しようとするものである。The present invention is intended to solve the above-mentioned problem of reduction in memory cell capacity due to higher integration.
問題点を解決するための手段
セル面積縮小に伴なうセル容量の減少を解決するために
、本発明では、キャパシター電極の表面積増大を図る。Means for Solving the Problems In order to solve the problem of a decrease in cell capacity due to a reduction in cell area, the present invention attempts to increase the surface area of the capacitor electrode.
その手段として、電荷蓄積電極としての拡散層に、その
拡散層の寸法に比べて十分小さな直径の柱状電極を形成
しその表面を誘電体薄膜で覆いさらにその上を導電体材
料で覆う。As a means for this, a columnar electrode having a diameter sufficiently smaller than the size of the diffusion layer is formed on the diffusion layer as a charge storage electrode, and the surface of the columnar electrode is covered with a dielectric thin film, which is further covered with a conductive material.
作用
柱状電極の直径が拡散層寸法に比べて十分小さいので多
数の柱状電極を拡散層上に立てることができる。その柱
状電極の側面がキャパシター電極として作用する。よっ
てキャパシター電極面積の増大が達せられる。Since the diameter of the working columnar electrode is sufficiently smaller than the size of the diffusion layer, a large number of columnar electrodes can be erected on the diffusion layer. The side surfaces of the columnar electrodes act as capacitor electrodes. Therefore, the area of the capacitor electrode can be increased.
実施例 本発明の一実施例を第１図を用いて説明する。Example An embodiment of the present invention will be described with reference to FIG.
Ｐ型シリコン基板１上に厚さ１ｏｎｍの二酸化硅素（５
ｉｎ２）から成るゲート絶縁膜２が成長していて、それ
を介して高濃度の砒素が含まれているポリシリコンから
成るゲート電極３が形成されている。このゲート電極３
はリード線として信号の読み出し、書込みを制御する。Silicon dioxide (5 nm) with a thickness of 1 onm is deposited on a P-type silicon substrate 1.
A gate insulating film 2 made of in2) is grown, and a gate electrode 3 made of polysilicon containing a high concentration of arsenic is formed through it. This gate electrode 3
controls reading and writing of signals as a lead wire.
ゲート電極により隔てられ、砒素を高濃度に含むｎ＋型
拡散層ＢとＳが形成されているが、ここでＢはアルミか
らなる金属配線４と接していてビット線の一部を構成し
、Ｓは電荷を蓄積する一方の電極である。ｎ＋型拡散層
Ｓ上には柱状電極６が多数垂直に立っている。N+ type diffusion layers B and S containing a high concentration of arsenic are formed, separated by a gate electrode, where B is in contact with a metal wiring 4 made of aluminum and forms part of a bit line, and S is one electrode that stores charge. A large number of columnar electrodes 6 stand vertically on the n+ type diffusion layer S.
柱状電極の側面・上面および拡散層Ｓ表面等はそれらの
熱酸化膜（ＳｉＯｚ＝８０ｎｍ）、ｅで覆われていて、
柱状電極６の間隙はポリシリコンから成る対向電極７で
埋められている。柱状電極５は拡散層Ｓと共に電荷蓄積
電極となっている。金属配線４とゲート３間は絶縁膜８
．９で電気的に分離されている。半導体基板１の一部に
はフィールド酸化膜１０が選択酸化法で形成されている
。The side surfaces and top surfaces of the columnar electrodes, the surface of the diffusion layer S, etc. are covered with a thermal oxide film (SiOz=80 nm), e.
The gap between the columnar electrodes 6 is filled with a counter electrode 7 made of polysilicon. The columnar electrode 5 and the diffusion layer S function as charge storage electrodes. An insulating film 8 is provided between the metal wiring 4 and the gate 3.
．． It is electrically isolated by 9. A field oxide film 10 is formed on a part of the semiconductor substrate 1 by a selective oxidation method.
柱状電極６の形成の一方法としてはＶＬＳ法（Ｖａｐｏ
ｒ −Ｌｉｑｕｉｄ −５ｏｌｉｄ ）が適用できる。One method for forming the columnar electrodes 6 is the VLS method (Vapor
r-Liquid-5olid) can be applied.
拡散層Ｓ上に例えばＦＩＢ法（Ｆｏｃｕｓｅｄ−Ｉｏｎ
Ｂｅａｍ）によりビーム径０．１μｍで金を打込み、そ
の上から気相成長法または真空蒸着法によりＳｌを堆積
させて半導体基板１を例えば１ｏｏｏ℃に加熱すると、
金が打込まれたところのみＳｉ結晶が柱状に成長する。For example, FIB method (Focused-Ion) is applied on the diffusion layer S.
When gold is implanted with a beam diameter of 0.1 μm using a beam), Sl is deposited thereon by vapor phase epitaxy or vacuum evaporation, and the semiconductor substrate 1 is heated to, for example, 100°C.
Si crystals grow in columnar shapes only where gold is implanted.
このとき柱の頂きに金が集中するので、所望の例えば０
．５μｍの高さに成長したあと頂き部分を王水で選択的
に除去し、熱酸化膜６を成長せしめる。At this time, the gold is concentrated at the top of the pillar, so the desired value, for example 0
．． After growing to a height of 5 μm, the top portion is selectively removed with aqua regia to grow a thermal oxide film 6.
柱状電極の半径をｒｌその高さをｈとし熱酸化膜を十分
薄いとして無視すると、所要基板表面にπ ｈ
対し柱状電極の側面はＲ＝７（７）倍に増大する。If the radius of the columnar electrode is rl and the height is h and the thermal oxide film is ignored as being sufficiently thin, the side surface of the columnar electrode will increase R=7 (7) times as much as the required substrate surface π h.
ｈ ＝０．５ μｍ Ｓｒ ＝０．０５ μｍのときＲ
＝１６倍となる。これは柱状電極を基盤状に並べたとき
であるが、第２図に示す様に六方稠密に配列した場倍と
なる。この面積増大率は、柱状電極の高さを高くシ、直
径をさらに小さくすることでより大きくできる。R when h = 0.5 μm Sr = 0.05 μm
=16 times. This is the case when the columnar electrodes are arranged in a base shape, but as shown in FIG. 2, they are arranged in a hexagonal dense manner. This area increase rate can be further increased by increasing the height of the columnar electrodes and further reducing the diameter.
発明の効果
実施例から明らかな様に本発明によれば、基板内に溝を
形成してキャパシター電極の面積増大させることに比べ
はるかに有効である。しかも本発明に於ては、技術の進
歩に伴なってより微細な加工が出来るようになれば、そ
れに応じて面積増大率が増加するので記憶のためのキャ
パシターの静電容量の減少は抑制される。よって従来１
６Ｍ〜６４Ｍビット／チップの集積度が限界と云はれて
いたダイナミックＲＡ Ｍ （Ｒａｎｄｏｍ−ムｃｃｅ
ｓｓＭｅｍｏｒｙ ）のより一層の集積度の向上に対し
て本発明の寄与するところは大である。Effects of the Invention As is clear from the embodiments, the present invention is much more effective than increasing the area of the capacitor electrode by forming a groove in the substrate. Moreover, in the present invention, if finer processing becomes possible as technology advances, the area increase rate will increase accordingly, so the decrease in the capacitance of the storage capacitor will be suppressed. Ru. Therefore, conventional 1
Dynamic RAM (Random RAM), whose density of 6M to 64M bits/chip was said to be the limit.
The present invention greatly contributes to further improving the degree of integration of ssMemory.
第１図は本発明の一実施例としてのメモリセルの断面図
、第２図は柱状電極の六方稠密配列状態を示す平面図で
ある。
１・・・・・・半導体基板、２・・・・・・ゲート絶縁
膜、３・・・・・・ゲート、４・・・・・・ビット線、
６・・・・・・柱状電極、ｅ・・・・・・誘電体薄膜、
７・・・・・・対向電極、５３．９１１０・・・・・・
絶縁膜、Ｂ・・・・・・ｎ十拡散層（ビット線）、Ｓ・
・・・・・ｎ＋拡散層（電荷蓄積電極）。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第２
図FIG. 1 is a sectional view of a memory cell as an embodiment of the present invention, and FIG. 2 is a plan view showing a hexagonal close-packed arrangement of columnar electrodes. 1... Semiconductor substrate, 2... Gate insulating film, 3... Gate, 4... Bit line,
6... Column electrode, e... Dielectric thin film,
7...Counter electrode, 53.9110...
Insulating film, B...n10 diffusion layer (bit line), S...
...n+ diffusion layer (charge storage electrode). Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
figure
Claims (2)
けられたワード線としてのゲート電極、上記ゲートによ
り隔てられ上記基板表面に形成された２導電型のビット
線としての拡散層Ｂおよび電荷蓄積電極としての拡散層
Ｓ、上記拡散層Ｓ表面に垂直に形成された複数個の導電
材料から成る柱状電極、上記柱状電極を覆う誘電体薄膜
を介して設けられ固定電位に接続された対向電極とを構
成要素として含んでなる半導体記憶装置。(1) A gate electrode as a word line provided on a 1-conductivity type semiconductor substrate via a gate insulating film, a diffusion layer B as a 2-conductivity type bit line separated by the gate and formed on the surface of the substrate, and A diffusion layer S as a charge storage electrode, a columnar electrode made of a plurality of conductive materials formed perpendicularly to the surface of the diffusion layer S, and an opposing electrode provided through a dielectric thin film covering the columnar electrode and connected to a fixed potential. A semiconductor memory device comprising an electrode as a component.
れている特許請求の範囲第１項記載の半導体記憶装置。(2) The semiconductor memory device according to claim 1, wherein the columnar electrodes are arranged in a hexagonal close-packed manner on the surface of the diffusion layer S.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61299413A JPS63151069A (en) | 1986-12-16 | 1986-12-16 | Semiconductive memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61299413A JPS63151069A (en) | 1986-12-16 | 1986-12-16 | Semiconductive memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63151069A true JPS63151069A (en) | 1988-06-23 |
Family
ID=17872236
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61299413A Pending JPS63151069A (en) | 1986-12-16 | 1986-12-16 | Semiconductive memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63151069A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02209765A (en) * | 1989-02-09 | 1990-08-21 | Mitsubishi Electric Corp | Semiconductor device |
| JPH03296264A (en) * | 1990-04-16 | 1991-12-26 | Nec Corp | Semiconductor memory cell and its manufacture |
-
1986
- 1986-12-16 JP JP61299413A patent/JPS63151069A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02209765A (en) * | 1989-02-09 | 1990-08-21 | Mitsubishi Electric Corp | Semiconductor device |
| JPH03296264A (en) * | 1990-04-16 | 1991-12-26 | Nec Corp | Semiconductor memory cell and its manufacture |
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