JPS63149918A - Picture data processing circuit - Google Patents

Abstract

PURPOSE:To quicken the coding processing by allowing a 1st coding means to apply the standard coding processing and to encode a code data converted into the standard code into other code unique to a manufacture further. CONSTITUTION:A read picture data is processed by a coding means 2 such as an exclusive LSI or the like by means of a 1st control means 4 and stored once in a buffer memory 5. Then the data stored in the buffer memory 5 is read by a 2nd control means 6 and other coding processing is applied. Thus, even if a coding means such as a general-purpose coding/decoding LSI capable of high speed coding processing is in use, it is possible to use the coding system unique to each manufacture in common and higher speed processing is attained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an image data processing circuit, that is, a circuit that encodes image data in a facsimile machine, etc., and more specifically, to an LSI capable of high-speed processing. The present invention relates to an image data processing circuit that converts image data into standard codes.

[Prior art]

When sending and receiving image information using a facsimile machine,
The amount of information actually transmitted and received is reduced by reading image information as image data of digital electrical signals and compressing and encoding this. Conventionally, this compression encoding process has generally been performed as a software process by a microcomputer.

However, in recent years, due to customer demands, the size of documents that can be processed by facsimile machines has gradually become larger and there has been a trend toward higher resolution. Therefore, not only the amount of information per document increases, but also the amount of information per scanning line.

On the other hand, there is a natural limit to the encoding processing speed of a microcomputer. Therefore, as mentioned above, a situation has arisen in which the software encoding process by a microcomputer cannot keep up with the increase in the amount of information per scanning line.

Under these circumstances, LSIs have been developed that can perform, for example, general-purpose standard (CCrTT standard, etc.) encoding processing at high speed, instead of the encoding processing that was conventionally performed by software using a microcomputer.

[Problem that the invention seeks to solve]

However, when using a dedicated LSI as described above, the problem of encoding processing speed is solved, but the encoding method is fixed to the method set in the hardware of that LSI. However, a problem arises in that, for example, when all one scanning line is a white signal, it is not possible to set a manufacturer's own code.

The present invention was made in view of these circumstances,
To provide an image data processing circuit that makes it possible to use a specific code for encoded data processed by an LSI dedicated to encoding processing in more specific cases, such as when all one scanning line is white data. With the goal.

[Means for solving problems]

In the image data processing circuit of the present invention, the read image data is processed by the encoding means such as a dedicated LSI by the first control means and temporarily stored in the buffer memory, and the data stored in the buffer memory is transferred to the second control means. The control means reads out the data and performs further encoding processing.

The image data processing circuit of the present invention includes a first encoding means for encoding image data according to a first encoding method, and a buffer memory for temporarily storing data encoded by the first encoding means. and a first control means for controlling writing of the data obtained by the first encoding means into the buffer memory, the first control means being connected to the buffer memory via a different bus, a second control means for controlling reading of data stored in the buffer memory; and a second control means for controlling reading of data stored in the buffer memory; It is characterized by comprising a second encoding means for encoding.

[Effect]

In the image data processing circuit of the present invention, the first encoding means performs, for example, standard encoding processing, and further converts the encoded data converted into the standard code into another code, for example, unique to the manufacturer. encoded.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on drawings showing embodiments thereof.

FIG. 1 is a block diagram showing the configuration of an image data processing circuit according to the present invention.

1 in the figure is picture 13! The reading circuit optically reads the original image at one scan level using, for example, a one-dimensional image sensor, converts it into a digital electrical signal, and supplies it to the encoding circuit 2.

The encoding circuit 2 uses, for example, an LSI that performs standard encoding processing such as the CC4TT standard on input image data in terms of hardware.

The data obtained by the encoding circuit 2 is transferred to the buffer memory 1J5 via the bus B1 by a direct memory access controller (hereinafter referred to as DMAC) 2.

Note that the above-mentioned image reading circuit 1. Encoding circuit 2 and DMA
C3 are both connected to a CPU4, which is a first control means, via a bus B1, and are controlled by this first CPU4.

The buffer memory 5 has a data area divided into two parts (A) and (B). For example, one data area has a first data area.
Encoding circuit 2 via bus B1 under the control of CPU 4 of
While the data from the other data area is being written, the data already stored in the other data area is written to the second CPU 6, which will be described later.
Both data areas are accessed alternately and in parallel by both CPUs 4 and 6, such that the data areas are read out via the second bus B2.

As mentioned above, the second CPU 6 is a second control means that reads data from the banoffer memory 5 via the bus B2, and also controls whether or not the data for one scanning line is all white, as described later. A second circuit makes a judgment and outputs a predetermined code if all are white, and if not, outputs the data read from the buffer memory 5 to the parallel/serial conversion circuit (hereinafter referred to as P/S circuit) 7. It also serves as an encoding means.

The P/3 circuit 7 converts the applied parallel data, for example 8-bit parallel data, into serial data and outputs it to the modulation/demodulation circuit 8.

The modulation/demodulation circuit 8 performs predetermined modulation processing on the serial data supplied from the 273 circuit 7, and outputs it to, for example, a general telephone line.

Regarding the operation of the apparatus of the present invention configured as described above, the content stored in the buffer memory 5 when transmitting a document, that is, the data after the image data has been subjected to general-purpose standard encoding processing by the encoding circuit 2. This will be explained with reference to the schematic diagram in FIG. 2 ra) showing the state of the data, and the schematic diagram in FIG.

The image data read by the image reading circuit 1 is encoded in units of each scanning line by an encoding circuit 2 which is a first encoding means using a general-purpose standard code decoding LSI.

The data encoded by the encoding circuit 2 is transferred to the DMA
C3 is transferred to the buffer memory 5 via the bus B1, and sequentially stored in its first data area (A). The first data area (A) of this buffer memory 5
When the first CPU 4 becomes full, the first CPU 4 outputs a code conversion processing request signal to the second CPU 6, and switches the address of the code transferred to the buffer memory 5 by the DMAC 5 to the second data area (B) side. . Thereby, the data encoded by the encoding circuit 2 is sequentially stored in the second data area (B) of the buffer memory 5.

On the other hand, the second CPU 6 starts the following process by receiving a code conversion processing request signal from the first CPU 4.

First, the second CPU 6 reads data from the first data area (A) of the buffer memory 5 and starts code conversion processing.

Here, it is assumed that data is stored in the first data area (A) of the buffer memory 5, for example, as shown in FIG. 2fa). That is, one scanning line completely white data from the first byte to the sixth byte consisting of a line end code EOL, one scanning line worth of white data D and a filler code Fi, a line end code EOL, and white/black mixed data. Leaf/B.

The 6th to 11th heights are configured with filler code Fi.
Assume that data containing both white and black data is stored in one scanning line of a byte.

Now, the second CPU 6 first starts with the buffer memory 5.
The data stored in the first data area (^) of the above-mentioned data from the first row end code F, O[, to before the filler code FiO, that is, from the first byte to the fourth byte, is successively stored. . Then, the read data is stored in advance in another memory (not shown), and a one-scan line all-white pattern is created, that is, one scan line of the read data is all white data nt1.
The data pattern when the value is 1 is compared sequentially. While the two match, the own data D is read from the beginning of that one scanning line.
Since the W indicates that the numbers are consecutive, the second CPU
6 does not output data to the 273 circuit 7.

After the above-described processing is performed, the first
If all the data of the I scanning line read from the data peak area (A) of 1 matches the 1 scanning line all-white pattern, that is, the 1 data read from the first data area (A) of the buffer memory 5
If all the data on the scanning line is white data DW,
The second CPU 6, as shown in FIG. The data length of Fi (which is shorter than the data length when white and black data are mixed in one scanning line) is sequentially output to the 278 circuit 7 in synchronization with the modulation processing speed of the modulation/demodulation circuit 8.

The data output to the H.273 circuit 7 is converted into serial data, modulated by the modulation/demodulation circuit 8, and sent to the telephone line.

During this time, the second CPU 6 detects the next row end code EOL from the first data area (A) of the buffer memory 5.

When the second CPt 16 detects the next line end code EOL, it performs the same processing as described above, but the data for the next one scanning line stored in the first data area (A) of the buffer memory 5 is white. - Black mixed data DW/B. Therefore, the second
The CPU 6 reads the data stored in the 6th and 7th bytes to the 11th byte and compares it with the one-scan line all-white pattern, but the two do not match halfway. This allows the second
The CPU 6 uses the line end code EOL.

■Line skip negation bit NLS indicating that white and black data are mixed in the scanning line and the data stored in the first data area (A) of the buffer memory 5 are sequentially sent to the P/S circuit 7. Output.

The data output to the P/3 circuit 7 is sent to the line from the modulation/demodulation circuit 8 in the same manner as described above.

- Image data is transmitted in units of one scanning line by sequentially performing any of the above processes in data units of one scanning line, but the first data area of the buffer memory 5 ( A) When the processing is completed for all the data stored in A), the second CPU 6
A signal indicating the end of conversion is output to U4, and the address of the data to be read is switched from the first data area (A) to the second data area (B).

On the other hand, when the first CPU 4 receives a signal indicating the end of conversion from the second CPU 6, it switches the data transfer from the encoding circuit 2 to the buffer memory 5 to the second data area (A) (nu1). .

By repeating the processing by the first CPU 4 and the second CPU 6 as described above, the first CPU 4 controls the standard encoding processing by the encoding circuit 2 and stores the data obtained as a result in the buffer memory 5. The second (: PII 6 processes in parallel the conversion of the general-purpose encoded data stored in the buffer memory 5 into a specific code and the transmission to the line. .

In the above embodiment, the encoding circuit 2, which is the first encoding means, performs encoding in hardware using LSI.
Although the second CP[+6, which is the second encoding means, is configured to perform encoding using software, it goes without saying that the opposite configuration may be used.
Alternatively, it goes without saying that both may be encoded using software.

(Effects) As detailed above, according to the present invention, even when an encoding means such as a general-purpose encoding/decoding LSI capable of high-speed encoding processing is used, each manufacturer's unique encoding method can be used. Since it becomes possible to use the image data processing circuit in combination, an image data processing circuit capable of higher speed processing is realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the circuit of the present invention, and FIG. 2 is a schematic diagram showing the contents of data processing. 1... Image reading circuit 2... Encoding circuit 4.
・・First CPU 5・Buffer memory 6・
...Second CPU Patent Applicant: Sanyo Electric Co., Ltd. Representative Patent Attorney: Noboru Kono Figure 2

Claims (1)

[Claims] 1. A first encoding means for encoding image data according to a first encoding method; and a buffer memory for temporarily storing data encoded by the first encoding means. , a first control means for controlling writing of data obtained by the first encoding means into the buffer memory; and the first control means is connected to the buffer memory by a different bus, and a second control means for controlling reading of data stored in the buffer memory; and when the data read by the second control means is in a predetermined state, the data is encoded according to a second encoding method. An image data processing circuit comprising: second encoding means for encoding.