JPS63149715A - Identifying method for reset input of processor - Google Patents

Abstract

PURPOSE:To discriminate whether a reset input is an initialization request signal or a power ON signal by storing specific data in a specific area of a volatile memory, reading out the contents of the volatile memory at the time of inputting a signal to a reset terminal and discriminating the contents. CONSTITUTION:A power ON signal is related to a power supply 6, and at the time of generating the power supply ON signal, the contents of a RAM 3 to be the volatile memory disappear. On the other hand, an in-prime signal is not related to the power supply 6 and the contents of the RAM 3 are held. When the contents of the specific area 3a in the RAM 3 are set up as fixed data and whether the contents of the specific area 3a in the RAM 3 are held fixed data or not is discriminated at the time of inputting a reset signal, whether the reset input is a power ON signal POS or an in-prime signal IPS can be discriminated.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Conventional technology Problems to be solved by the invention Means for solving the problems (Fig. 1) Example of operation (a) Example of one embodiment Description (Figure 2) (bl Description of other embodiments Effects of the invention [Summary]) In a system where an initial setting request signal and a power-on signal are input to the reset terminal of a processor, Data is stored and when a signal is input to the reset terminal, the contents of a specific area of the volatile memory are read and determined to determine whether the reset input is an initial setting request signal or a power-on signal. thing.

[Industrial application field]

The present invention relates to a reset input identification method capable of determining the type of signal input to a reset terminal of a processor, and in particular to a reset input identification method for a processor capable of distinguishing between a power-on signal and an initial setting request signal (in-prime signal). Regarding the method.

In systems using processors, the advent of non-volatile memory has made it possible to have various initial states.

There are three types of means for transitioning to this initial state: hardware, software, and power-on, and it is necessary to transition to various initial states depending on these.

[Conventional technology]

Taking the printer device shown in FIG. 3 as an example of a system using a processor, as shown in FIG. A random access memory (RAM) 3 is connected to a data/address bus 7a.

A driver 4 is connected to the CPUI via a data bus 7b, and the driver 4 has a dot print head) '5a,
The head space motor 5b and line feed motor 5C are connected.

In order to supply these power sources, a power supply 6 is provided, and commercial power is supplied to the power supply 6 via a switch SW, and the operating voltage (
5V) is supplied to the CPUI, ROM2, RAM3, driver 4, etc.

The CPU is provided with a reset terminal (interrupt terminal) R3T, which receives a power on/off signal from the power supply 6 and an in-prime signal IPS from a host unit or the like as an interrupt.

When the CPU 1 receives a signal at the reset terminal R3T, it does not distinguish between the signals, clears the RAM 3 as an initial state, and executes a space initial (return movement to the initial position) of the head, as shown in FIG. 3(B). That's what I do.

[Problem that the invention seeks to solve]

In such a conventional method, since the power on/off signal and the in-prime signal IPS are input to the same reset terminal as a reset signal, they cannot be distinguished.

Therefore, when there is a design convenience in which it is desired to perform one initial setting process using the power-on signal and another initial setting process using the in-prime signal IPS, a problem arises in that this cannot be performed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a processor reset input identification method that can distinguish between a power-on signal and an in-prime signal input to a single interrupt terminal.

[Means for solving problems]

FIG. 1 is a diagram explaining the principle of the present invention.

1A, the same parts as those shown in FIG. 3 are indicated by the same symbols, and 3a is a specific area of the RAM (volatile memory) 3.

In the present invention, as shown in FIG. 1(B), when a signal is input to the reset terminal R3T of the CPU1, the CPU
3, and determines whether the read content is the same as the fixed data, and identifies whether the reset signal is the power-on signal PO8 or the in-prime signal IPS.

[Effect]

The present invention focuses on the action of the power source 6.

The power-on signal is related to the power supply 6, and when the power-on signal is generated, the contents of RAM3, which is a volatile memory, are erased.On the other hand, the in-prime signal is not related to the power supply 6, and the contents of RAM3 are lost.
The contents of M3 are retained.

Therefore, the contents of the specific area 3a of the RAM 3 are set as fixed data, and when the reset signal is input, the specific area 3a of the RAM 3
The power-on signal PO8 or the in-prime signal IPS is determined by determining whether the contents of the
can be identified.

〔Example〕

(a) Description of one embodiment FIG. 2 is a detailed explanatory diagram of the present invention.

In the figure, the same parts as those shown in Figs. 1 and 3 are indicated by the same symbols, and 2a is a fixed data storage area of ROM 2, which stores fixed data for identifying the reset signal. Reference numeral 3b is a registration area of the RAM 3, which is used to store registered contents, character patterns, etc.

The operation of the embodiment in FIG. 2 will be explained with reference to the principle flowchart in FIG. 1(B).

When the CPUI receives a reset signal from the reset terminal R3T, the CPUI receives the reset signal from the reset terminal R3T via the address/data bus 7a.
Read the contents of the specific area 3a of AM3.

Next, the CPU is fixed data storage area 2a of ROM2.
The fixed data is read out via the address/data bus 7a and compared with the read contents of the specific area 3a.

Through this comparison, if the CPU determines that the read content of RAM3 is the same as the read fixed data of ROM2, the input reset signal is the in-prime signal, and if it determines that the content is not the same, the input calibercent signal is the power-on signal. identify with.

That is, since the power-on signal is generated when the power is turned on after the power is turned off, the fingering memory RA is generated when the power is turned off.
The contents of M3 have been deleted and cannot match 80M2. On the other hand, since the in-prime signal is not related to power on/off, the contents of RAM3 are retained.
It cannot match with ROM2.

When the large reset signal is determined to be a power-on signal, power-on reset processing is performed, that is, clearing RAM3, headspace, etc., and furthermore, in order to identify the reset signal, RA
The fixed data is written to the specific area 3a of M3, and the initial processing is completed.

On the other hand, if the input reset signal is determined to be an in-prime signal, initialization processing includes clearing the registers in the CPUI and the registers of the driver 4, and performing a headspace operation.

Therefore, the RAM 3 is not cleared, the contents of the registration area 3b are not erased, and the registered character patterns etc. can be used from now on.

(b) Description of Other Embodiments In the above-described embodiments, a printer device was used as an example, but the present invention is not limited to this, and any system having a processor may be used.

Further, the initial processing is not limited to the embodiment, and various other methods can be applied.

Although the present invention has been described above using examples, the present invention can be modified in various ways according to the gist of the present invention, and these are not excluded from the present invention.

[Effects of the Invention] As explained above, according to the present invention, it is possible to distinguish between two types of reset signals input to one reset terminal of a CPU, that is, a power-on signal and other in-prime signals. This enables separate initial (or reset) processing.

Moreover, the method for this purpose can also be easily and easily realized, which is an excellent practical effect.

[Brief explanation of the drawing]

FIG. 1 is a diagram explaining the principle of the present invention, FIG. 2 is a detailed explanatory diagram of the present invention, FIG. 3 is an explanatory diagram of the prior art. In the figure, 1-processor; 2.-ROM. 3-RA M (volatile memory), 6...-Power supply.

Claims (1)

[Claims] Comprising a volatile memory (3) and a processor (1), a power-on signal and an initial setting request signal are transmitted to the processor (1).
), in which the processor (1) reads the contents of a specific area of the memory (3) in response to receiving a signal input to the reset terminal, and inputs the contents in accordance with the read contents. A method for identifying a reset input for a processor, comprising identifying whether a signal is a power-on signal or an initialization request signal.