JPS63148631A - Method of forming flat film on wafer substrate - Google Patents
Method of forming flat film on wafer substrateInfo
- Publication number
- JPS63148631A JPS63148631A JP62285648A JP28564887A JPS63148631A JP S63148631 A JPS63148631 A JP S63148631A JP 62285648 A JP62285648 A JP 62285648A JP 28564887 A JP28564887 A JP 28564887A JP S63148631 A JPS63148631 A JP S63148631A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- solvent
- oven
- forming
- polymer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 28
- 239000000758 substrate Substances 0.000 title claims description 12
- 239000002904 solvent Substances 0.000 claims description 31
- 229920000642 polymer Polymers 0.000 claims description 17
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 238000000576 coating method Methods 0.000 claims description 15
- 239000011248 coating agent Substances 0.000 claims description 10
- 230000008034 disappearance Effects 0.000 claims description 6
- 230000008021 deposition Effects 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 claims description 5
- 238000009423 ventilation Methods 0.000 claims description 4
- 238000010304 firing Methods 0.000 claims description 2
- 238000013022 venting Methods 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 35
- 239000004065 semiconductor Substances 0.000 description 7
- 239000011324 bead Substances 0.000 description 5
- 238000000151 deposition Methods 0.000 description 5
- 239000011521 glass Substances 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 238000009987 spinning Methods 0.000 description 2
- DKPFZGUDAPQIHT-UHFFFAOYSA-N Butyl acetate Natural products CCCCOC(C)=O DKPFZGUDAPQIHT-UHFFFAOYSA-N 0.000 description 1
- VGGSQFUCUMXWEO-UHFFFAOYSA-N Ethene Chemical compound C=C VGGSQFUCUMXWEO-UHFFFAOYSA-N 0.000 description 1
- 239000005977 Ethylene Substances 0.000 description 1
- LRHPLDYGYMQRHN-UHFFFAOYSA-N N-Butanol Chemical group CCCCO LRHPLDYGYMQRHN-UHFFFAOYSA-N 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920003986 novolac Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- -1 polysiloxanes Polymers 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/16—Coating processes; Apparatus therefor
- G03F7/168—Finishing the coated layer, e.g. drying, baking, soaking
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/312—Organic layers, e.g. photoresist
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Application Of Or Painting With Fluid Materials (AREA)
- Formation Of Insulating Films (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
この発明はウェハ基板上に平坦な被膜を形成する方法に
関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to a method of forming a flat coating on a wafer substrate.
従来の技術
従来の半導体素子の製造工程においては１通常５ミクロ
ン以下の厚さの薄いホトレジスト層をスピン法によって
複数個のウェハ上に順次被着している。感光性レジスト
は適当なマスクを介して露光されて現像され、得られた
レジストパターンはエツチングまたは被着法によって金
属層へ転写される。BACKGROUND OF THE INVENTION In a conventional semiconductor device manufacturing process, thin photoresist layers, typically less than 5 microns thick, are sequentially deposited onto a plurality of wafers by a spinning method. The photosensitive resist is exposed to light through a suitable mask, developed, and the resulting resist pattern is transferred to the metal layer by etching or deposition techniques.
発明が解決しようとする問題点
用途によっては、厚さ５〜５０ミクロンもしくはそれ以
上のレジスト層を使う必要があることが判明している。PROBLEMS SOLVED BY THE INVENTION Depending on the application, it has been found necessary to use a resist layer with a thickness of 5 to 50 microns or more.
しかしながら、厚くなればなるほどウェハに一様に被着
するのがむずかしくなる。ウェハ面の凹凸形状によって
厚さが変わり、さらにウェハの縁部に近づくほどレジス
トのビードの厚さが増大するという重大な問題がある。However, the thicker the layer, the more difficult it is to uniformly coat the wafer. There is a serious problem in that the thickness changes depending on the uneven shape of the wafer surface, and the thickness of the resist bead increases as it approaches the edge of the wafer.
この発明は、新規なりフロー技術によって半導体または
他のウェハ上に一様な厚さのホトレジスト被膜または他
のポリマ被膜を得る方法を意図するものである。この発
明の方法は、すでに大きな凹凸形状をもつウェハを平坦
化するの、に特に有用である。The present invention is directed to a method of obtaining uniform thickness photoresist or other polymer coatings on semiconductor or other wafers by a novel flow technique. The method of the invention is particularly useful for planarizing wafers that already have large topography.
この発明の目的は、半導体または他のウェハ上の大きな
凹凸形状に亘って、極めて小さな縁部ビード幅で一様な
厚さのホトレジスト被膜専たは他のポリマ被膜を形成し
得る方法を提供するにある。It is an object of this invention to provide a method by which photoresist coatings or other polymeric coatings can be formed of uniform thickness over large features on semiconductor or other wafers with extremely small edge bead widths. It is in.
問題点を解決するための手段
この発明によると、電子的ウェハ上に平坦な被膜を形成
する方法は、溶剤を含むポリマをスピン被着によってウ
ェハ上に形成し、ポリマが乾燥する前に、ポリマ被着ウ
ェハをオーブン内に配置する。溶剤蒸気の圧力を保つこ
とによって溶剤消失を制御しながらウェハを加熱し、溶
剤を緩慢に消失させてポリマ表面を平坦化する。SUMMARY OF THE INVENTION In accordance with the present invention, a method for forming a planar coating on an electronic wafer includes forming a solvent-containing polymer onto the wafer by spin deposition, and before the polymer dries. Place the deposited wafer in the oven. The wafer is heated while controlling the disappearance of the solvent by maintaining the pressure of the solvent vapor to slowly dissipate the solvent and planarize the polymer surface.
その後、ウェハをオーブンから取り出し、標準的な対流
焼付がま内で焼成サイクルを施こす。The wafer is then removed from the oven and subjected to a bake cycle in a standard convection bake oven.
熱流出を減らして平坦化の効率を高めるために、オーブ
ン内においてウェハを複数個の小径先端ピンで支持する
。To reduce heat loss and increase planarization efficiency, the wafer is supported in the oven with a plurality of small diameter tipped pins.
さらに、この発明によると、半導体素子上に平坦なホト
レジスト層を形成する方法は、溶剤を含むホトレジスト
層をスピン被着によって素子の表面上に形成する。ホト
レジスト層が乾燥する前に、オーブン内で素子を約９０
℃で約１０分間加熱し、その際溶剤蒸気の圧力によって
オーブンによる溶剤消失制御と溶剤消失の緩慢化を行な
ってレジスト層の表面を平坦化する。その後、素子をオ
ーブンから取り出し、標準的な対流焼付がまに配置して
焼成サイクルを施こす。Further in accordance with the present invention, a method for forming a planar photoresist layer on a semiconductor device includes forming a photoresist layer containing a solvent on the surface of the device by spin deposition. Place the device in an oven for approximately 90 minutes before the photoresist layer dries.
C. for about 10 minutes, and at this time, the pressure of the solvent vapor is used to control and slow down the disappearance of the solvent in an oven, thereby flattening the surface of the resist layer. The device is then removed from the oven and placed in a standard convection bake oven for a baking cycle.
一実施態様では、オーブンは、溶剤蒸気の通気を制御す
る通気孔を有し、この通気孔は底縁に隣接して設けられ
る。しかしながら、上記オーブンとして閉じたオーブン
を用い、外部ソースから溶剤の分圧を供給することもで
きる。In one embodiment, the oven has a vent for controlling venting of solvent vapor, the vent being located adjacent the bottom edge. However, it is also possible to use a closed oven as the oven and supply the partial pressure of the solvent from an external source.
実施例 以下、実施例を用いてこの発明の詳細な説明する。Example The present invention will be described in detail below using examples.
以下の説明では厚いホトレジスト層を半導体上に形成す
るものについて例示するが、この発明の方法は他の電子
的ウェハ上に他のポリマの平坦な被膜を得るのにも有用
である。Although the following discussion is illustrative of forming thick photoresist layers on semiconductors, the method of the invention is also useful for obtaining flat coatings of other polymers on other electronic wafers.
前述のように、従来の半導体素子の製造工程においては
、通常５ミクロン以下の厚さの薄いホトレジスト層をス
ピン法によって複数個のウェハ上に順次被着している。As mentioned above, in conventional semiconductor device manufacturing processes, thin photoresist layers, typically less than 5 microns thick, are sequentially deposited onto a plurality of wafers by a spinning method.
被膜が厚くなるほど形成がむずかしく、まして一様な被
膜を得るのは困難である。ウェハ面の凹凸形状によって
厚さが変わり、さらにウェハの縁部に近づくほどホトレ
ジストのビードの厚さが増大するという重大な問題があ
る。The thicker the coating, the more difficult it is to form, and even more difficult to obtain a uniform coating. There is a serious problem in that the thickness varies depending on the uneven shape of the wafer surface, and the thickness of the photoresist bead increases as it approaches the edge of the wafer.
この発明の方法は、半導体のようなウェハに厚さ５〜５
０ミクロンの被膜を被着するのに特に有用である。この
発明の方法によって、１０１．６−ｍ（４インチ）直径
のウェハ面の９９％に亘って、３０ミクロン厚のホトレ
ジスト層を±２％の厚さばらつきで形成することができ
た。The method of this invention applies to wafers such as semiconductors with a thickness of 5 to 5 mm.
It is particularly useful for depositing 0 micron coatings. The method of the present invention was able to form a 30 micron thick layer of photoresist over 99% of the surface of a 4 inch diameter wafer with a thickness variation of ±2%.
刻−
以下の方法は２６ミクロン厚のノボラック樹脂ホトレジ
スト被膜形成に用いた。まず、第１図に示すように、５
秒、１２００ｒｐｍの通常のスピン被着法によって容器
１工からのホトレジスト１０をウェハ１２の表面へ供給
して厚さ２６ミクロンの被膜を形成した。なお、スピン
被着法ではウェハ１２の縁部に大きなビード１３が生じ
る。ホトレジスト１０が乾燥、硬化し始める前に、ウェ
ハ１２を平坦化オーブン１４内のピン１６上に載置する
。オーブン１４内でウェハ１２はガラスカバ−１８内部
に支持される。このガラスカバー１８は通気孔２０を有
し、該通気孔は好ましくはカバー１８の底縁に隣接して
設けられる。図示のオーブンはカバー１８を囲んでいる
が、カバー１８内に配置した加熱コイルをオーブンとし
て用いることもできる。The following method was used to form a 26 micron thick novolac resin photoresist coating. First, as shown in Figure 1, 5
Photoresist 10 from container 1 was applied to the surface of wafer 12 to form a 26 micron thick coating using a conventional spin deposition process at 1200 rpm for 20 seconds. Note that the spin deposition method produces large beads 13 at the edges of the wafer 12. Before photoresist 10 begins to dry and harden, wafer 12 is placed on pins 16 in planarization oven 14. Within oven 14, wafer 12 is supported within a glass cover 18. The glass cover 18 has a vent 20 which is preferably located adjacent the bottom edge of the cover 18. Although the illustrated oven encloses a cover 18, a heating coil disposed within the cover 18 can also be used as an oven.
温度およびレジスト系溶剤（たとえばアルコール、ブチ
ルアセテート、エチレン、ポリイミド）の蒸気濃度を制
御する。この処理の初期においてレジスト１０は液状で
あるから、レジストｌＯの上方の溶剤蒸気の分圧によっ
て溶剤消失率を制御すればレジストの硬化を遅らせるこ
とができる。この例では、オーブン１４内でウェハ１２
を９０℃で約１０分間加熱した。ガラスカバー１８の容
積が約７３８ＣＩ！（４５立方インチ）、通気孔２０の
高さが２゜３７ｍｍ （０，０９３インチ）のときレジ
スト１０からの溶剤消失率が良好に制御される。なお、
レジストがゆっくりと硬化する間にウェハ１２の縁から
は溶剤が急速に消失し、その結果、従来の急激な硬化の
場合よりも狭いビードがウェハ１２の縁に得られる。Control the temperature and resist solvent (eg, alcohol, butyl acetate, ethylene, polyimide) vapor concentration. Since the resist 10 is in a liquid state at the beginning of this process, curing of the resist can be delayed by controlling the solvent disappearance rate by controlling the partial pressure of the solvent vapor above the resist 10. In this example, the wafer 12 is placed inside the oven 14.
was heated at 90°C for about 10 minutes. The volume of the glass cover 18 is approximately 738 CI! (45 cubic inches), and when the height of the vent hole 20 is 2.37 mm (0.093 inch), the rate of solvent disappearance from the resist 10 is well controlled. In addition,
The solvent rapidly disappears from the edge of the wafer 12 while the resist slowly cures, resulting in a narrower bead at the edge of the wafer 12 than with conventional rapid curing.
さらに、レジスト１０の領域内でウェハ１２にかなり高
い凸状部があっても、それに対応するレジスト１０の表
面部分は大きく盛り上らないですむので、レジスト１０
をゆっくりと硬化することにより良好な平坦化が達成さ
れる。Furthermore, even if the wafer 12 has a fairly high convex portion within the area of the resist 10, the corresponding surface portion of the resist 10 does not need to swell significantly.
Good planarization is achieved by slow curing.
一般に、厚いレジスト１０内には充分な溶剤が含まれる
のでウェハ１２の上方の溶剤分圧を維持することができ
る。カバー１８の底縁周りの通気孔２０の高さと、カバ
ー１８の内部空間容積との関係を例えばねじ３０で調整
すれば最適な溶剤分圧が得られる。Generally, sufficient solvent is contained within the thick resist 10 to maintain a partial solvent pressure above the wafer 12. An optimal solvent partial pressure can be obtained by adjusting the relationship between the height of the vent hole 20 around the bottom edge of the cover 18 and the internal space volume of the cover 18 using, for example, the screw 30.
オーブン内でウェハ１２をピン１６上に載置しているの
で、ウェハ１２の空間支持が行なえ該ウェハは一様に加
熱される。また、支持用の３個のピンは小径であるから
、ウェハ１２からの熱の流出を制限して乾燥を一様化し
、平坦化を助長する。さらにまた、ピン１６の先端は極
く細であり、レジスト１０の表面形状に影響しない。Since the wafer 12 is placed on the pins 16 in the oven, spatial support of the wafer 12 is provided and the wafer is uniformly heated. Furthermore, since the three supporting pins have a small diameter, they limit the outflow of heat from the wafer 12, uniformize drying, and promote flattening. Furthermore, the tip of the pin 16 is extremely thin and does not affect the surface shape of the resist 10.
オーブン１４内で１０分間加熱した後、ウェハ１２をオ
ーブン１４から取り出し、標準的な対流焼付がま内で８
０℃、３０分間の焼成サイクルを施こす。After heating in oven 14 for 10 minutes, wafer 12 is removed from oven 14 and placed in a standard convection baking oven for 8 minutes.
A firing cycle is performed at 0° C. for 30 minutes.
オーブン１４を閉じた系として、外部ソースから溶剤の
分圧を供給し外部へ通気するようにすることもできる。Oven 14 can also be a closed system, with partial pressure of solvent supplied from an external source and vented to the outside.
この場合は、カバー１８に接続した溶剤蒸気圧ライン２
２と通気ライン２４とを設けることができる。In this case, the solvent vapor pressure line 2 connected to the cover 18
2 and a ventilation line 24 can be provided.
上記ではホトレジストの厚い層を形成するものについて
述べたが、この発明の方法は、ホトレジストと同様な流
れ特性および硬化特性を持つポリマたとえばポリイミド
やポリシロキサンにも適用できる。Although described above with respect to forming thick layers of photoresist, the method of the present invention is also applicable to polymers such as polyimides and polysiloxanes that have flow and curing properties similar to photoresists.
ゆえに、この発明は既述の諸口的を達成し、かつ他の本
来の利点をよく達成するものである。Thus, the present invention achieves the objectives set forth above and also satisfies other inherent advantages.
この発明の上記の実施例は説明のために用いたものであ
り、その工程の細部はこの発明の特許請求の範囲内で当
業者によって種々と変形できる。The above-described embodiments of the invention are used for illustrative purposes, and the details of the process may be varied by those skilled in the art without departing from the scope of the claims of the invention.
第１図は、この発明におけるスピン被着工程の概略説明
図、第２図は、同上における平坦な表面被膜を形成する
ためにオーブン内に設けられる部分的に閉じたカバーの
平面図、第３図は第２図の３−３線に沿う断面図である
。
ｌＯ・・・ポリマ １２・・・ウェハ基板１
４・・・オーブン １６・・・ピン崩１叉
馬３図FIG. 1 is a schematic explanatory diagram of the spin deposition process according to the present invention; FIG. 2 is a plan view of a partially closed cover installed in the oven to form a flat surface coating; and FIG. The figure is a sectional view taken along line 3-3 in FIG. 2. lO...Polymer 12...Wafer substrate 1
4... Oven 16... Pinkoro 1 Tsuma 3 figures
Claims (1)
上に形成する工程と、ポリマが乾燥する前に、ポリマ被
着ウェハを一様に加熱するためにオーブン内において該
ウェハを複数個のピンで支持する工程と、溶剤蒸気の圧
力を保つことによって溶剤消失を制御しながらウェハを
加熱し溶剤を緩慢に消失させてポリマ表面を平坦化する
工程と、ウェハを焼付がま内に配置して焼成サイクルを
施こす工程とを有するウェハ基板上に平坦な被膜を形成
する方法。 ２、特許請求の範囲第１項において、オーブン内でウェ
ハを細い先端のピン上に支持させる平坦被膜形成方法。 ３、特許請求の範囲第１項において、スピン被着の厚さ
が５ミクロン以上である平坦被膜形成方法。 ４、溶剤を含むホトレジスト層をスピン被着によってウ
ェハ基板上に形成する工程と、該層が乾燥する前に、ウ
ェハを複数個のピンで支持し、オーブン内の通気カバー
内で該ウェハを約９０℃で約１０分間加熱し、その際溶
剤蒸気の圧力を保つことによってオーブンによる溶剤消
失制御を行う工程と、溶剤を緩慢に消失させてレジスト
層の表面を平坦化する工程と、得られた素子を対流焼付
がま内に配置して焼成サイクルを施こす工程とを有する
ウェハ基板上に平坦な被膜を形成する方法。 ５、特許請求の範囲第４項において、通気カバーはこの
カバーの底縁に隣接する通気孔を有する平坦被膜形成方
法。 ６、特許請求の範囲第５項において、オーブン内でウェ
ハを細い先端のピン上に支持させる平坦被膜形成方法。 ７、溶剤を含み厚さが５ミクロン以上のポリマをスピン
被着によってウェハ基板上に形成する工程と、ポリマが
乾燥する前に、ポリマ被着ウェハを一様に加熱するため
にオーブン内において該ウェハを複数個のピン先端で支
持する工程と、ウェハを加熱する工程と、溶剤蒸気を緩
慢に通気しながら圧力を保つことによって溶剤消失を制
御し、溶剤を緩慢に消失させてポリマ表面を平坦化する
工程と、ウェハを対流焼付がま内に配置して焼成サイク
ルを施こす工程とを有するウェハ基板上に平坦な被膜を
形成する方法。 ８、特許請求の範囲第７項において、ポリマをウェハに
約１２００ｒｐｍで約５秒間スピン被着させる平坦被膜
形成方法。[Claims] 1. Forming a polymer containing a solvent on a wafer substrate by spin deposition, and before the polymer dries, placing the wafer in an oven to uniformly heat the polymer-coated wafer. The process involves supporting the wafer with multiple pins, heating the wafer while controlling the disappearance of the solvent by maintaining the pressure of the solvent vapor to slowly dissipate the solvent, and flattening the polymer surface. 1. A method for forming a flat coating on a wafer substrate, the method comprising the steps of: disposing the wafer substrate within the wafer substrate and subjecting the wafer substrate to a firing cycle; 2. A method for forming a flat film according to claim 1, in which the wafer is supported on pins with thin tips in an oven. 3. A method for forming a flat film according to claim 1, wherein the thickness of the spin-deposited film is 5 microns or more. 4. Forming a layer of photoresist containing a solvent on the wafer substrate by spin deposition, and before the layer dries, supporting the wafer with a plurality of pins and placing the wafer in a ventilation cover in an oven for approximately A step of heating at 90° C. for about 10 minutes and controlling the disappearance of the solvent using an oven by maintaining the pressure of the solvent vapor during the process, and a step of slowly dissipating the solvent to flatten the surface of the resist layer. 1. A method for forming a flat coating on a wafer substrate comprising placing the device in a convection baking oven and subjecting it to a baking cycle. 5. The method for forming a flat film according to claim 4, wherein the ventilation cover has ventilation holes adjacent to the bottom edge of the cover. 6. A method for forming a flat film according to claim 5, wherein the wafer is supported on pins with narrow tips in an oven. 7. Forming a solvent-containing polymer with a thickness of 5 microns or more onto the wafer substrate by spin deposition, and before the polymer dries, placing the polymer-coated wafer in an oven to uniformly heat the polymer-coated wafer. Solvent dissipation is controlled by supporting the wafer with the tips of multiple pins, heating the wafer, and maintaining pressure while slowly venting solvent vapor, and flattening the polymer surface by slowly dissipating the solvent. 1. A method for forming a flat coating on a wafer substrate comprising the steps of: converting the wafer into a convection baking oven; and placing the wafer in a convection baking oven and subjecting it to a baking cycle. 8. The method of claim 7, wherein the polymer is spun onto the wafer at about 1200 rpm for about 5 seconds.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US930166 | 1986-11-13 | ||
| US06/930,166 US4794021A (en) | 1986-11-13 | 1986-11-13 | Method of providing a planarized polymer coating on a substrate wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63148631A true JPS63148631A (en) | 1988-06-21 |
Family
ID=25459008
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62285648A Pending JPS63148631A (en) | 1986-11-13 | 1987-11-13 | Method of forming flat film on wafer substrate |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4794021A (en) |
| EP (1) | EP0268116B1 (en) |
| JP (1) | JPS63148631A (en) |
| DE (1) | DE3766940D1 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0275378A (en) * | 1988-09-08 | 1990-03-15 | Teru Kyushu Kk | Coating method |
| JPH06236871A (en) * | 1993-01-18 | 1994-08-23 | Internatl Business Mach Corp <Ibm> | Formation of insulation layer having smooth surface |
| JPH07135171A (en) * | 1993-05-20 | 1995-05-23 | Tokyo Electron Ltd | Method and device of treating coated film |
| WO2004109779A1 (en) * | 2003-06-06 | 2004-12-16 | Tokyo Electron Limited | Method for improving surface roughness of processed film of substrate and apparatus for processing substrate |
| JP2010186929A (en) * | 2009-02-13 | 2010-08-26 | Tokyo Electron Ltd | Substrate processing apparatus and substrate processing method |
| JP2021119001A (en) * | 2014-09-25 | 2021-08-12 | ズス・マイクロテック・リソグラフィ・ゲゼルシャフト・ミット・ベシュレンクテル・ハフツングSuss MicroTec Lithography GmbH | Method for coating substrate with lacquer, and device for planarizing lacquer layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5298288A (en) * | 1991-02-14 | 1994-03-29 | Microelectronics And Computer Technology Corporation | Coating a heat curable liquid dielectric on a substrate |
| US5622747A (en) * | 1991-09-18 | 1997-04-22 | National Semiconductor Corporation | Method for dispensing a layer of photoresist on a wafer without spinning the wafer |
| JPH0734890B2 (en) * | 1991-10-29 | 1995-04-19 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Spin coating method |
| US5358740A (en) * | 1992-06-24 | 1994-10-25 | Massachusetts Institute Of Technology | Method for low pressure spin coating and low pressure spin coating apparatus |
| US5378511A (en) * | 1993-03-22 | 1995-01-03 | International Business Machines Corporation | Material-saving resist spinner and process |
| TW268905B (en) * | 1993-05-20 | 1996-01-21 | Tokyo Electron Co Ltd | |
| US6124215A (en) * | 1997-10-06 | 2000-09-26 | Chartered Semiconductor Manufacturing Ltd. | Apparatus and method for planarization of spin-on materials |
| US6383289B2 (en) | 1997-12-16 | 2002-05-07 | The University Of North Carolina At Chapel Hill | Apparatus for liquid carbon dioxide systems |
| US6001418A (en) | 1997-12-16 | 1999-12-14 | The University Of North Carolina At Chapel Hill | Spin coating method and apparatus for liquid carbon dioxide systems |
| US6207546B1 (en) | 1998-08-28 | 2001-03-27 | Taiwan Semiconductor Manufacturing Company | Prevent passivation from keyhole damage and resist extrusion by a crosslinking mechanism |
| US6143644A (en) * | 1998-09-17 | 2000-11-07 | Taiwan Semiconductor Manufacturing Company | Method to prevent passivation from keyhole damage and resist extrusion |
| US7344970B2 (en) * | 2002-04-11 | 2008-03-18 | Shipley Company, L.L.C. | Plating method |
| US6716285B1 (en) | 2002-10-23 | 2004-04-06 | The United States Of America As Represented By The Secretary Of The Air Force | Spin coating of substrate with chemical |
| US7323417B2 (en) * | 2004-09-21 | 2008-01-29 | Molecular Imprints, Inc. | Method of forming a recessed structure employing a reverse tone process |
| JP2005161168A (en) * | 2003-12-01 | 2005-06-23 | Tokyo Ohka Kogyo Co Ltd | Film forming method |
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| US7259102B2 (en) * | 2005-09-30 | 2007-08-21 | Molecular Imprints, Inc. | Etching technique to planarize a multi-layer structure |
| US7802978B2 (en) * | 2006-04-03 | 2010-09-28 | Molecular Imprints, Inc. | Imprinting of partial fields at the edge of the wafer |
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| US10656525B2 (en) * | 2017-09-01 | 2020-05-19 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Photoresist baking apparatus |
| JP2022525165A (en) | 2019-03-12 | 2022-05-11 | ディジレンズ インコーポレイテッド | Holographic Waveguide Backlights and Related Manufacturing Methods |
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Family Cites Families (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US569160A (en) * | 1896-10-13 | Edward w | ||
| JPS5819350B2 (en) * | 1976-04-08 | 1983-04-18 | 富士写真フイルム株式会社 | Spin coating method |
| US4068019A (en) * | 1976-11-08 | 1978-01-10 | International Business Machines Corporation | Spin coating process for prevention of edge buildup |
| DE2743011C2 (en) * | 1977-09-23 | 1982-06-03 | Siemens AG, 1000 Berlin und 8000 München | Arrangement for applying a light-sensitive lacquer layer to a semiconductor wafer |
| US4347302A (en) * | 1980-06-06 | 1982-08-31 | Alexander Gotman | Process for applying a thin coating in liquid form and subsequently drying it |
| NL8200666A (en) * | 1982-02-19 | 1983-09-16 | Philips Nv | TRANSMISSION CIRCUIT FOR AN ELECTRONIC TELEPHONE. |
| US4468411A (en) * | 1982-04-05 | 1984-08-28 | Motorola, Inc. | Method for providing alpha particle protection for an integrated circuit die |
| US4510176A (en) * | 1983-09-26 | 1985-04-09 | At&T Bell Laboratories | Removal of coating from periphery of a semiconductor wafer |
| JPS60226125A (en) * | 1984-04-25 | 1985-11-11 | Matsushita Electronics Corp | Formation of resist film |
| US4562100A (en) * | 1984-09-14 | 1985-12-31 | E. I. Du Pont De Nemours And Company | Polyimide coating compositions from diesterified anhydride and aromatic diamine |
-
1986
- 1986-11-13 US US06/930,166 patent/US4794021A/en not_active Expired - Fee Related
-
1987
- 1987-10-28 DE DE8787115855T patent/DE3766940D1/en not_active Expired - Fee Related
- 1987-10-28 EP EP87115855A patent/EP0268116B1/en not_active Expired - Lifetime
- 1987-11-13 JP JP62285648A patent/JPS63148631A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0275378A (en) * | 1988-09-08 | 1990-03-15 | Teru Kyushu Kk | Coating method |
| JPH06236871A (en) * | 1993-01-18 | 1994-08-23 | Internatl Business Mach Corp <Ibm> | Formation of insulation layer having smooth surface |
| JPH07135171A (en) * | 1993-05-20 | 1995-05-23 | Tokyo Electron Ltd | Method and device of treating coated film |
| WO2004109779A1 (en) * | 2003-06-06 | 2004-12-16 | Tokyo Electron Limited | Method for improving surface roughness of processed film of substrate and apparatus for processing substrate |
| US7875420B2 (en) | 2003-06-06 | 2011-01-25 | Tokyo Electron Limited | Method for improving surface roughness of processed film of substrate and apparatus for processing substrate |
| US8646403B2 (en) | 2003-06-06 | 2014-02-11 | Tokyo Electron Limited | Method for improving surface roughness of processed film of substrate and apparatus for processing substrate |
| JP2010186929A (en) * | 2009-02-13 | 2010-08-26 | Tokyo Electron Ltd | Substrate processing apparatus and substrate processing method |
| JP4748742B2 (en) * | 2009-02-13 | 2011-08-17 | 東京エレクトロン株式会社 | Substrate processing apparatus and substrate processing method |
| JP2021119001A (en) * | 2014-09-25 | 2021-08-12 | ズス・マイクロテック・リソグラフィ・ゲゼルシャフト・ミット・ベシュレンクテル・ハフツングSuss MicroTec Lithography GmbH | Method for coating substrate with lacquer, and device for planarizing lacquer layer |
Also Published As
| Publication number | Publication date |
|---|---|
| US4794021A (en) | 1988-12-27 |
| DE3766940D1 (en) | 1991-02-07 |
| EP0268116B1 (en) | 1991-01-02 |
| EP0268116A1 (en) | 1988-05-25 |
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