JPS63147836U - - Google Patents

Info

Publication number
JPS63147836U
JPS63147836U JP4021587U JP4021587U JPS63147836U JP S63147836 U JPS63147836 U JP S63147836U JP 4021587 U JP4021587 U JP 4021587U JP 4021587 U JP4021587 U JP 4021587U JP S63147836 U JPS63147836 U JP S63147836U
Authority
JP
Japan
Prior art keywords
lead
integrated circuit
circuit device
spacing
predetermined terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4021587U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4021587U priority Critical patent/JPS63147836U/ja
Publication of JPS63147836U publication Critical patent/JPS63147836U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP4021587U 1987-03-19 1987-03-19 Pending JPS63147836U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4021587U JPS63147836U (zh) 1987-03-19 1987-03-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4021587U JPS63147836U (zh) 1987-03-19 1987-03-19

Publications (1)

Publication Number Publication Date
JPS63147836U true JPS63147836U (zh) 1988-09-29

Family

ID=30854104

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4021587U Pending JPS63147836U (zh) 1987-03-19 1987-03-19

Country Status (1)

Country Link
JP (1) JPS63147836U (zh)

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