JPS63146437A - Wafer surface thermal stress disposition suppressing system - Google Patents

Abstract

PURPOSE:To largely shorten the rising period of a new process by predicting the generation of a thermal stress disposition on the basis of thermal stress induced when a wafer row is inserted and removed, and optimizing the process parameter of a heat treatment. CONSTITUTION:The transient characteristic of temperature distribution on a wafer and the thermal stress distribution characteristic of the wafer are calculated by a computer simulation on the basis of a predetermined physical model 4. A thermal stress evaluation graph in which a transition curve representing the transition of the thermal stress on the wafer surface with respect to the temperature of the wafer and a yield stress curve of the wafer are drawn on the basis of the calculated characteristics is formed. A generation limit is presumed and evaluated by the formed graph. Thus, the thermal stress disposition based on the thermal stress induced when the wafer row is inserted and removed is predicted. The process parameter of the heat treatment is so optimized as to fall the thermal stress within the predicted limit.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for predicting the occurrence of thermal stress dislocations including crystal defects in a high-temperature heat treatment step of a semiconductor manufacturing process. The present invention relates to an in-plane thermal stress dislocation generation suppression method suitable for optimizing process parameters so that thermal stress can be suppressed within the limit of crystal defect generation during failure analysis of wafers.

[Conventional technology]

The method of predicting the occurrence of crystal defects for each heat treatment process condition using a wafer eight-plane thermal stress analysis model in a semiconductor oxidation/diffusion device, as in the present invention, is unprecedented. About Journal
Of Applied Fizukus Volume 56 10 (198
4) Pages 2922 to 2929 (J, Appl
, Phys, 56(10), 1984 (pp, 2
922-2929). However, what is being evaluated here?

This is a case of single-wafer lamp annealing in which wafers are processed one by one, and the in-plane temperature distribution and thermal stress distribution of the wafer are given by analytical formulas assuming axial symmetry.

Therefore, in the case of an ordinary cylindrical resistance heating electric furnace that is currently commonly used, that is, an oxidation/diffusion device that processes rows of about 50 to 100 wafers in batches, Their transient temperature characteristics and thermal stress characteristics vary widely and require unique model development.

[Intermediate point to be solved by the invention] The above-mentioned conventional technology is related to setting process conditions using a thermal stress analysis model for single-wafer lamp annealing, and processes rows of about 50 to 100 wafers at a time. There were some interlayers that could not be applied to the evaluation of the occurrence of crystal defects for batch processing methods.

An object of the present invention is to insert and insert a row of wafers into an oxidation/diffusion device in a process involving high-temperature heat treatment in a semiconductor manufacturing process.
It is an object of the present invention to provide a method for determining process parameters such as wafer row insertion speed so that thermal stress induced during extraction can be suppressed within the limit of generation of thermal stress dislocations such as crystal defects.

[Means for resolving interstices]

The above purpose is to calculate the transient characteristics of the wafer in-plane temperature, which changes depending on process conditions such as wafer row insertion speed, tube wall temperature profile, and wafer spacing, and the wafer in-plane thermal stress using the temperature distribution as a loading condition. By constructing a simulation model and comparing its thermal stress transition curve with the wafer's own yield stress curve, which has strong temperature dependence, on a thermal stress evaluation graph with wafer temperature on the horizontal axis and thermal stress on the vertical axis. achieved.

[Effect]

The wafer temperature transient analysis model, which estimates the in-plane temperature distribution of wafers that transiently occurs when a row of wafers is inserted into an oxidation/diffusion device, describes the heat balance mainly due to radiation to the row of wafers and the boat jig that supports them. It is constructed using a system of simultaneous partial differential equations, and calculates the in-plane temperature distribution for each wafer and at each time according to changes in process parameters such as wafer row movement speed, tube wall temperature, and wafer spacing. Details of this model can be found in the Journal of the Institute of Electronics and Communication Engineers (C)
Vol. 68, No. 6, (1985), pp. 425-432
Discussed on page.

The thermal stress analysis model uses the in-plane temperature distribution of the wafer determined from the wafer temperature transient analysis model as the thermal load condition.
The thermal stress generated there is calculated by the finite element method using triangular constant strain elements formulated as a plane stress problem. Furthermore, the plane stress component (σX
tσyy.

τxy) to calculate the resolved shear stress taking into account the slip plane and slip axis of the silicon crystal. Details of this model, Ra is the proceedings of J Nis Nis Chi
International Conference Schlei (19
1986) Pages 509 to 513 (Proc,
J S S T I nt, , Conf, J
(1986) pp. 509-513).

Finally, the thermal stress evaluation graph is a semi-logarithmic graph that depicts the yield stress curve of the wafer itself, which has strong temperature dependence, with the wafer temperature on the horizontal axis and the logarithm of the stress value on the vertical axis. The thermal stress transition curve associated with the insertion of wafer rows under these conditions is obtained by smoothly connecting the plot points of the thermal stress values calculated using the model mentioned above, and the thermal stress transition curve and yield stress curve are From the comparison, it is easy to predict the occurrence of crystal defects.

Furthermore, the amount of calculations described above is enormous, and in order to proceed with the analysis, it is very effective to construct an interactive crystal defect generation evaluation computer system (CAE) that includes a graphic terminal. In other words, a series of simulation models such as a wafer temperature transient analysis model and a wafer internal thermal stress analysis model are installed in a computer, and the results of these calculations are stored in a file (a storage device) and a thermal stress evaluation graph is created. If the process conditions can be created on the screen of a terminal, thermal stress transition curves corresponding to changes in process conditions can be immediately obtained, and process conditions can be optimized interactively.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 14.

FIG. 12 shows the overall configuration of an oxidation/diffusion device 120 to which the present invention is applied.

In FIG. 12, 101 is a cylindrical reaction tube that provides a heat source necessary for heat treatment of wafers, 102 is a soaking tube, 103 is a heating element, 104 is a wafer to be processed, 105 is a boat jig that supports the wafer, and 106 is a reaction tube. A device for measuring the temperature of the tube, 107 is an automatic insertion/drawing device a, TOS is a temperature control unit that arbitrarily realizes the temperature distribution in the axial direction of the reaction tube, 109 is a doping system for supplying processing gas into the reaction tube, il
O is a control unit that comprehensively controls each component described above, and is realized by a microprocessor or the like.

In the process involving high-temperature heat treatment such as oxidation, diffusion, annealing, etc., a large number of wafers 104 arranged on a boat 105 are transferred to a reaction tube 108 maintained at a predetermined temperature by an automatic insertion/drawing device 107. After being inserted into the reaction tube and treated in a gas atmosphere supplied from the doping system 109, it is pulled out of the reaction tube.

First, the operation of the semiconductor heat treatment process CAE system as a crystal defect occurrence evaluation tool built on the computer shown in FIG. 1 will be explained.

Process conditions to be evaluated, i.e. wafer diameter,
Simulation conditions such as tube wall temperature, wafer row insertion speed, and wafer spacing are input from the graphic terminal 2 and set in the simulation condition storage file 7. Under these simulation conditions, the in-plane temperature distribution of each wafer at each time, which occurs transiently during the insertion of a wafer row, is calculated from Transactions of the Institute of Electronics and Communication Engineers (C), Vol. 68 (1985), No. 42.
The calculation is performed using the wafer temperature transient analysis model 3 shown in detail on pages 5 to 432, and the results are written to the storage file 6.Furthermore, using this in-plane temperature calculation result, the procedure・Chi International Conference Schlei (1986)
Pages 509 to 513 (Proc, J S 5T
Int, Conf, July (1986)
The thermal stress corresponding to the slip system of the silicon crystal is calculated using the wafer in-plane thermal stress analysis model 4 shown in detail in pp. 509-513), and the result is written to the storage file 5. The numerical calculations by the simulation model calculation unit 1 for the set process conditions were completed, and a thermal stress evaluation graph as shown in FIG. 2 created on the screen of the graphic terminal 2 was used. Proceed to evaluation of occurrence of crystal defects0 This graph is on a semi-logarithmic graph giving the yield stress curve (σ!E(T))10 of silicon material, which has a strong temperature dependence, and indicates that defects occur transiently when inserting a row of wafers. The transition of thermal stress as the wafer temperature rises can be measured using the stored file containing the thermal stress calculation results.

The curves are drawn as shown in curves 11 to 14 in FIG. 2, corresponding to the designated position within the wafer and the slip system. The results here focus on the thermal stress generated at the diagonally upper peripheral position in the 45@ direction of the central wafer in the wafer row, where crystal defects are likely to occur.

The thermal stress transition curve 12 shown in FIG. 2 is compared to the curve 11 when the tube wall temperature is lowered by 100°C, and the thermal stress transition curve 13 is compared to the curve 11 when the wafer spacing is doubled.
The thermal stress transition curve 14 corresponds to the process conditions when the wafer row insertion speed is increased five times compared to the curve 13. From this result, the thermal stress transition curves 1 and 14 exceed the yield stress curve 10, and the thermal stress transition curves 12 and 13 do not exceed the yield stress curve 10. That is, curves 1, 14
Crystal defects occur under process conditions corresponding to curve 1.
It can be predicted that this will not occur under process conditions corresponding to 2.13. In addition, tube wall temperature, wafer row insertion speed,
Sensitivity analysis of each process parameter of wafer spacing can be clearly understood as a relative positional relationship with the yield stress curve 10.

Therefore, among the above three process parameters,
In situations where one is fixed and cannot be changed, the other two
The five evaluation graphs can be effectively used for problems such as how to set two parameters. For example, under the process conditions corresponding to the thermal stress transition curve 11 described above, it is predicted that the yield stress will be exceeded and crystal defects will occur.
It is assumed that process conditions in which crystal defects do not occur are realized by an optimal combination of two other parameters under the constraint that the wafer row insertion speed is fixed. Here, optimal means the tube wall temperature.

The smaller the insertion speed and the larger the wafer spacing, the lower the thermal stress level, but since this operation reduces throughput, it is important to consider this trade-off. means.

Regarding the point that a decrease in tube wall temperature decreases throughput, in the current heat treatment process, when inserting a row of wafers, the tube wall temperature is lowered by about 100 degrees Celsius than the processing temperature to relieve thermal stress, and then the insertion is completed. A ramping method is used in which the temperature is then raised to the processing temperature, which means that a dead time is required to raise the temperature to the processing temperature by the amount of temperature drop during insertion.

Now, returning to the above problem, in FIG. 2, when only the tube wall temperature is changed and is lowered by 100°C with respect to the thermal stress level all, the thermal stress level is determined by the thermal stress transition curve 12.
To the left with respect to the yield stress curve 10, i.e.,
A big shift towards safety. On the other hand, when only the wafer spacing is changed and doubled, the thermal stress level shifts downward with respect to the yield stress curve 10, as shown in the thermal stress transition curve 13, but the tube wall temperature Especially compared to thermal stress transition curve 12, which lowered the temperature to the safe side.

The yield stress curve approaches 10 in the region where the wafer temperature is high. Considering the combination of these two process conditions and its effect on throughput, for the former, the time required to raise the tube wall temperature by 100°C,
Regarding the latter, the number of sheets processed in batches will be halved. Furthermore, by similarly performing the above evaluation on the thermal stress evaluation graph when both the tube wall temperature and the wafer spacing are changed, the optimal process conditions can be rationally selected.

On the other hand, another use of the thermal stress evaluation graph is to estimate the yield stress curve of the silicon wafer itself. Wafers flowing through an actual semiconductor manufacturing line are subjected to repeated stress and thermal history during many heat treatment processes, and their yield stress is expected to decrease. The method for estimating this yield stress is shown in Figure 3. Thermal stress transition curve 21 in the figure
24 shows the thermal stress obtained by simulation for a silicon wafer that has been previously subjected to a certain heat treatment, corresponding to the process conditions under which an experiment was conducted to evaluate the occurrence of crystal defects. (Curves 2, 22).

(Curves 23 and 24) are obtained under the same conditions for two of the three process parameters. Also 1
Curve 21, curve 221, curve 23, and curve 24 each correspond to the case where the remaining one process parameter is slightly varied.

Now, if crystal defects occur under the process conditions of thermal stress transition curves 2 and 23, but they do not occur under thermal stress transition curves 22 and 24, the yield stress curve of the wafer under consideration here would be normal. Yield stress curve of silicon material 1
curve 21, curve 22, and curve 23.
It can be estimated on this thermal stress evaluation graph that the curve shown by the broken line 20 passing between and the curve 24 is given.

Also, when starting up new processes such as increasing the diameter of wafers,
If there is no existing experimental data, use data on the occurrence of crystal defects at conventional wafer diameters and perform the following procedure.
By estimating the yield stress curve of the new process, the number of experiments required to establish process conditions that suppress thermal stress within the thermal stress dislocation generation limit during the heat treatment process during start-up can be significantly reduced, and the results can be backed up by physical models. Rational optimization of process parameters can be achieved.

For example, as data on the occurrence of crystal defects at a conventional wafer diameter, the in-plane distribution is shown in the region 3 surrounded by the broken line in Figure 4.
0, the thermal stress transition curves 41 to 43 corresponding to the wafer in-plane devices (α to γ) 31 to 33 marked with X in the same area are drawn as shown in - in Fig. 5. Data on the occurrence of crystal defects at each position obtained through simulation, that is, occurrence at α, boundary between occurrence/non-occurrence at β, and γ
Then, the yield stress curve 40 may be estimated on the thermal stress evaluation graph shown in FIG. 5 so as to match the non-generated crystal.

As shown above, when starting up a new process, only the wafer diameter is thicker, the fabrication process specifications, and the strength characteristics of the wafers before treatment, i.e., the oxygen content, bulk defect density, substrate impurity type, etc., are the same. , using the yield stress curve estimated above.

It is possible to predict whether or not crystal defects will occur in the wafer plane under process parameters such as the wafer insertion speed in a certain heat treatment step of this manufacturing process. For example, as shown in FIG. 6, when the insertion speed and tube wall temperature are fixed, it can be determined by simulation how much the wafer spacing should be increased to prevent crystal defects from occurring.

An example of a simulation of the wafer temperature transition is shown in FIG. 13. This is a tube wall temperature of 950℃ and an insertion speed of 100c.
＋*/min, wafer spacing of 9.21, and a row of φ150■■ wafers are inserted into the reaction tube. This shows a bird track diagram of the temperature distribution 50 occurring within the wafer surface at 1 minute and 30 seconds after insertion. , the horizontal axes X and Y indicate the distance in the X-axis direction and the Y-axis direction of the wafer surface, and the vertical axis indicates the wafer temperature.

Furthermore, the wafer in-plane thermal stress model can be constructed as follows. First, the wafer temperature changes by about 100°C from room temperature during the insertion process, and is dynamic, but does not show a sudden temperature change that would indicate a thermal shock phenomenon, and is handled quasi-statically. It is assumed that the in-plane temperature distribution occurring at each time is in a steady state. Furthermore, since the wafer is an isotropic homogeneous elastic body and its thickness is sufficiently small compared to the wafer radius, the thermal stress (σ) = (σ work, σ a) as a plane stress layer when subjected to the above thermal load.

τxy) is formulated by the finite element method using triangular constant strain elements. The matrix equation to be satisfied for each element is given by the following equation.

[K](δ) =-(F) tzo (1)
Here, (K) is the stiffness matrix of the element, (δ) is the displacement column vector, (F) RO is the column vector of the equivalent nodal force due to thermal strain applied to each node, and the wafer temperature from the settling temperature Initial strain (EO) due to change amount ΔT = −(α
ΔT, αΔT, 0). α indicates the coefficient of thermal expansion. The wafer temperature of each element is the temperature Tw 1t Tw J I Tw obtained for each mesh intersection using the wafer temperature transient analysis model using the difference method, as shown in FIG. 14 which gives an example of finite element division. The average value of k was used. Furthermore, since the temperature distribution within the wafer surface is symmetrical with respect to the y-axis, as shown in FIG. 14, half of the wafer plane with respect to the y-axis was divided into finite elements and used as the calculation target.

From this, the X-direction displacement U of the element contact points on the y-axis, which is the axis of symmetry, is all 0, and in order to eliminate rigid body changes in the y-direction, the contact point between the wafer 141 and the boat 142 is fixed at the fixed point 14.
3, and a boundary condition in which the displacement V in the y direction is set to 0 was assumed.

Under this boundary condition, all elements are assembled using equation (1). By solving the simultaneous-dimensional multidimensional equations for unknown displacement and finding the strain (ε), the thermal stress (σ) for each element can be calculated from the linear relationship between stress and strain when the following initial strain is present.

(σ) = (Dl ((ε)−(εo))
(2) Here, [D] represents an elastic stress-strain matrix including Young's modulus E and Poisson's ratio Y.

In addition, in comparison with the yield stress, considering the slip plane (111) of the silicon wafer and the slip axis <110>, it corresponds to five independent slip systems calculated from the thermal stress (σ) as shown in the following equation. Decomposed shear stress +s11~1ssl
must be used.

According to the embodiments described above, optimization of the wafer heat treatment process conditions can be realized on a computer by using a simulation model, so that it can be applied to larger diameter wafers or changes in process specifications.

Mass production lines can be started up quickly.

An example of estimating the yield stress curve of a target wafer has been described above, and now a method for determining it will be described in more detail based on the experimental formula.

The temperature-dependent yield stress σ2 (
The empirical formula for T) is given as equation (4).

Here, T is the absolute temperature, k is the Boltzmann constant, U is the activation energy regarding the sliding motion of the crystal, C is the strain rate, and n and C are experimental constants.

Here, the uncertainty that the yield stress itself changes for each target process specification due to the number of heat treatments mentioned earlier, the strength characteristics of the wafer before treatment, etc. can be rationalized by combining the above experimental parameters n, C1, and strain rate e. It is necessary to explain the From its physical meaning, the strain rate e corresponds to the time rate of change of thermal stress generated within the wafer plane, and is one of the process parameters, which is the rate of temperature rise of the wafer when the wafer row is inserted into the reaction tube. It depends greatly on the insertion speed. Therefore, rather than being a factor that changes the yield stress curve due to the number of heat treatments in the target process, etc., it is a parameter that should be adjusted in response to large changes in the insertion speed range.

Next, the characteristics of the yield stress curve when the experimental parameters n and C were changed are shown in FIGS. 7 and 8, respectively.

In both figures, yield stress curves 100 to 102 corresponding to three different manufacturing processes, such as product targets and wafer substrate impurity types, which have already been estimated, are also shown. The appearance of the yield stress curves corresponding to the changes in n and C shown in Figures 7 and 8 differs greatly on this evaluation graph, and the C dependence is more pronounced in the high temperature region than the n dependence. It has high sensitivity. In other words, as is clear from the following equation (5), the stress value taken on the vertical axis on the thermal stress evaluation graph given as a semi-logarithm is only a parallel movement in the vertical direction.

When n changes, the wafer temperature T
A high temperature region where n is large corresponds to a decrease in the sensitivity of n.

It can be seen that the changes in the yield stress curves 100 to 102 corresponding to the three target manufacturing processes shown in FIGS. 7 and 8 can be well explained by the changes in the experimental parameter C shown in FIG.

In addition, the strain rate C was fixed at 0.25X10-5/see in both figures. This value corresponds to the strain rate in the wafer row insertion speed range that is currently commonly used, as will be discussed below in the influence of strain rate on yield stress.

Finally, we will discuss the influence of strain rate C on yield stress. The strain rate e corresponds to the rate at which the load stress is applied, and as shown in the experimental formula (1) above, this value changes the yield stress curve as shown in Figure 9. The yield stress value clearly indicates the order of magnitude of this value.

Now, the strain rate e on wafers when inserting a row of wafers into the oxidation/diffusion equipment that is the subject of this article depends heavily on the speed at which thermal stress is applied transiently within the wafer surface, that is, the insertion speed of the wafer row. do. The relationship between this wafer row insertion speed and strain rate is expressed using the wafer spacing as a parameter.

It is shown in Figure 1O. Here, the strain rate is calculated by using the finite element method to calculate the equivalent lateral force due to temperature change during stress measurement, that is, the initial strain e. It was represented by the time rate of change C.

Here, 11yi2 represents time, and coo and co2 represent the initial strain at 1 hour t1 and the initial strain at 1 hour t2, respectively.

As is clear from Figure 1O, the insertion speed is 10~30c+
Insertion speed 50c+ compared to strain rate in the region of s/min
The strain rate at a time of 1 minute or more increases by about 3 to 10 times.

As an example, the prediction evaluation of the occurrence of out-of-stock defects in consideration of the change in strain rate for a φ150 wafer and the experimental verification results will be described below.

FIG. 11 shows a thermal stress evaluation graph at this time.

In the figure, the thermal stress transition surface @110 corresponds to a process condition where the insertion speed is low and the strain rate e = 0.39X10-'/see, and the thermal stress transition curve 111 has a high insertion speed and corresponds to the process condition of 6=, 3X10-'/see. '/see is supported. Also,
The yield stress curve 112 has been estimated for the former strain rate region.

The yield stress curve 113 is calculated by the change in strain rate under both conditions (3
, 3 times), and shows a yield stress curve modified to evaluate the occurrence of crystal defects in the latter case. As is clear from this figure, under both conditions, if the estimated yield stress curve 112 is taken as the boundary line for the occurrence of crystal defects, the thermal stress transition curve 111 has a larger yield stress surface 1tt2 than the thermal stress transition curve 110. Therefore, the occurrence of crystal defects should be greater in the latter than in the former. However, in the experimental results, a clear slip line was observed locally in the 45@ direction of the wafer under the former process condition where the strain rate was low, but no slip line was observed at all under the latter process condition where the strain rate was high. Not done. In other words, no thermal stress dislocation occurred. This experimental fact can be well explained by evaluating the yield stress curve 113 obtained by increasing the yield stress curve when the strain rate is high by the increase.

Therefore, the wafer row insertion speed is greatly reduced (e.g.,
It is important to evaluate the occurrence of crystal defects while paying attention to the fact that the stress curve itself may be increasing under process conditions that significantly change the strain rate. At that time, the change in the yield stress curve can be determined by modifying the yield stress σff('r) given by the equation (4), taking into account the change in the strain rate obtained from the equation (6), as described above. .

〔Effect of the invention〕

According to the present invention, in the heat treatment process of the semiconductor manufacturing process, the occurrence of crystal defects due to heat treatment that occurs when inserting a row of wafers into an oxidation/diffusion device can be evaluated on a computer using a physical model instead of an experiment that requires a large amount of manpower. Since it is easy to carry out, new processes can be launched to accommodate larger diameter wafers, etc.

This has the effect of significantly shortening the period for failure analysis for process-induced defects.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of an evaluation system when the present invention is realized on a computer, Figure 2 is an example of a thermal stress evaluation graph for evaluating the occurrence of crystal defects, and Figure 3 is an example of estimating a yield stress curve. Figure 4 is a diagram showing the distribution of crystal defects in the wafer plane, Figure 5 is a diagram showing an example of estimating the yield stress curve using the in-plane distribution of crystal defects in Figure 4, and Figure 6 is the diagram showing the distribution of crystal defects in the wafer plane. Figures 7 to 9 are diagrams showing the dependence of the level on the wafer spacing, and Figures 7 to 9 are diagrams showing the dependence on the experimental constants n, C, and strain rate in the experimental equation of the yield stress curve, respectively. Figure 10 is the diagram showing the dependence on the wafer row insertion rate and strain. Figure 11 is a velocity relationship diagram, and Figure 1 is a diagram showing an example of crystal defect generation prediction evaluation considering the strain rate dependence of yield stress.
Figure 2 is an overall configuration diagram of an oxidation diffusion device to which the present invention is applied, Figure 13 is a diagram showing an example of the change in well temperature distribution calculated by a wafer temperature transient analysis model, and Figure 14 is a diagram based on a well in-plane thermal stress model. FIG. 3 is a diagram showing an example of finite elements for half a wafer.弗δbutsufu muriseb)

Claims (1)

[Scope of Claims] 1. A process for predicting the occurrence of thermal stress dislocation based on thermal stress induced during insertion/extraction of wafer rows in a high-temperature heat treatment step of a semiconductor manufacturing process, and a process for predicting the occurrence of thermal stress dislocation within the predicted generation limit. A method for suppressing the occurrence of thermal stress dislocations within a wafer surface, comprising: optimizing the process parameters of heat treatment so as to suppress the occurrence of thermal stress dislocations in the wafer surface. 2. The above prediction process involves calculating the transient characteristics of the wafer in-plane temperature distribution and the wafer in-plane thermal stress distribution characteristics by computer simulation based on a predetermined physical model, and the process of calculating the wafer temperature distribution with respect to the wafer temperature based on the calculated characteristics. The process of creating a thermal stress evaluation graph by drawing a transition curve representing the in-plane thermal stress transition and the yield stress curve of the wafer, and the process of estimating and evaluating the above-mentioned generation limit from the created graph. In-plane thermal stress dislocation suppression method. 3. The above-mentioned physical model is the wafer in-plane thermal stress dislocation generation suppression method of item 2, which consists of a wafer temperature transient analysis model and a wafer in-plane thermal stress analysis model. 4. Method for suppressing the occurrence of thermal stress dislocations within the wafer surface described in item 2, which estimates the yield stress curve of the wafer itself in the target process on the evaluation graph using the existing experimental data regarding the occurrence or non-occurrence of thermal stress dislocations. .