JP2690902B2 - Method for suppressing thermal stress dislocation generation in the wafer surface - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for predicting the occurrence of thermal stress dislocations including crystal defects in a high temperature heat treatment step of a semiconductor manufacturing process,
In particular, the present invention relates to a wafer in-plane thermal stress dislocation generation suppression method suitable for optimizing process parameters so that thermal stress can be suppressed within a crystal defect generation limit when a new process is started and a semiconductor product is analyzed for defects. [Prior Art] There is no other method of predicting the occurrence of crystal defects for each heat treatment process condition by a wafer in-plane thermal stress analysis model in a semiconductor oxidation / diffusion apparatus as in the present invention.
However, for its model calculation principle,
Of Applied Physcus Volume 56 10 (1984) No. 2922
Pages 2929 (J.Appl.Phys.56 (10), 1984 (pp.2922
−2929). However, the evaluation target here is the case of a single-wafer type lamp annealing in which the wafers are processed one by one, and the in-plane temperature distribution of the wafer and the thermal stress distribution are given by an analytical formula assuming axial symmetry. ing. Therefore, in the case of an ordinary cylindrical resistance heating electric furnace that is most commonly used at present, that is, in the case of an oxidation / diffusion device that batch-processes about 50 to 100 wafer rows, Transient temperature characteristics and thermal stress characteristics are very different and require original model development. [Problems to be solved by the invention] The above-mentioned conventional technology relates to process condition determination by a thermal stress analysis model for single-wafer lamp annealing, and processes a wafer row of about 50 to 100 wafers at a time. There is a problem that it cannot be applied to the evaluation of the occurrence of crystal defects in the batch method. An object of the present invention is to suppress the thermal stress induced at the time of inserting / drawing a wafer row to / from an oxidation / diffusion device in a process accompanied by high temperature heat treatment in a semiconductor manufacturing process within a generation limit of thermal stress dislocations such as crystal defects. Another object of the present invention is to provide a method for determining process parameters such as wafer row insertion speed. [Means for Solving Problems] The above-mentioned object is that the transient characteristics of the in-plane temperature of the wafer, which changes depending on the process conditions such as the wafer row insertion speed, the tube wall temperature profile, and the wafer interval, and the temperature distribution are the load conditions. A consistent simulation model for calculating in-plane thermal stress of the wafer was constructed, and the yield stress curve of the wafer itself having a strong thermal stress transition curve and temperature dependence was taken, the horizontal axis shows the wafer temperature, and the vertical axis shows the thermal stress. It is achieved by comparing on a thermal stress evaluation graph. [Operation] The wafer temperature transient analysis model, which estimates the temperature distribution in the wafer plane that occurs transiently when the wafer row is inserted into the oxidation / diffusion device, is based on the thermal radiation mainly to the wafer row and the boat jig that supports it. It is constructed by a system of simultaneous partial differential equations describing the balance, and the in-plane temperature distribution at each wafer and each time is calculated according to changes in the process parameters such as wafer row moving speed, pipe wall temperature, and wafer interval. For details of this model, see IEICE Transactions (C)
Vol. 68, No. 6, (1985) pp. 425-432. The thermal stress analysis model is a finite element that uses the triangular constant strain element that is the thermal stress condition that is the in-plane temperature distribution of the wafer determined from the above wafer temperature transient analysis model, and the thermal stress generated there is formulated as a plane stress problem. Calculate by the method. Furthermore, the plane stress component (σx
x, σyy, τxy) is used to calculate the decomposition shear stress considering the slip plane and slip axis of the silicon crystal. For details of this model, see Proceedings of JSS International Conference Jurai (19
(86) pp. 509 to 513 (Proc.JSST Int.Conf.July
(1986) pp.509-513). Finally, the thermal stress evaluation graph is a semi-logarithmic graph in which the horizontal axis represents the wafer temperature and the vertical axis represents the logarithm of the stress value, in which the yield stress curve of the wafer itself having a strong temperature dependence is drawn.
The transition of thermal stress due to wafer row insertion under given process conditions is a smooth connection of plot points of thermal stress values calculated by the model mentioned above. The occurrence of crystal defects can be easily predicted by comparison with the yield stress curve. Furthermore, the above-mentioned calculation amount becomes enormous, and in order to proceed with the analysis, it is very effective to construct an interactive computer system for crystal defect evaluation (CAE) including a graphic terminal. That is, a series of simulation models of a wafer temperature transient analysis model and a wafer in-plane thermal stress analysis model are installed in a computer, and the settlement results of these can be stored in a file (memory device), and the thermal stress evaluation graph can be stored in a graphic terminal. If it can be created on the screen, a thermal stress transition curve corresponding to changes in process conditions can be immediately obtained, and process conditions can be optimized interactively. [Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1 to 14. FIG. 12 shows the overall structure of an oxidation / diffusion device 120 to which the present invention is applied. In FIG. 12, 101 is a cylindrical reaction tube that provides a heat source necessary for heat treatment of a wafer, 102 is a soaking tube, 103 is a heating element,
104 is a wafer to be processed, 105 is a boat jig that supports the wafer, 106 is a device for measuring the temperature of the reaction tube, 107 is an automatic insertion / withdrawal device, and 108 is a temperature control for arbitrarily realizing the axial temperature distribution of the reaction tube. Reference numeral 109 is a doping system for supplying a processing gas into the reaction tube, and reference numeral 110 is a control unit for comprehensively controlling the above-mentioned components, which is realized by a microprocessor or the like. In a process involving high-temperature heat treatment such as oxidation, diffusion, and annealing, which is a target here, a large number of wafers 104 lined up on a boat 105 of a reaction tube 108 kept at a predetermined temperature by an automatic insertion / drawing device 107. It is inserted into the inside of the reactor, treated in a gas atmosphere supplied from the doping system 109, and then drawn out of the reaction tube. First, the operation of the semiconductor heat treatment process CAE system as a crystal defect generation evaluation tool built on the computer shown in FIG. 1 will be described. The process condition to be evaluated, that is, the wafer diameter,
Simulation conditions such as tube wall temperature, wafer row insertion speed, and wafer interval are input from the graphic terminal 2 and set in the simulation condition storage file 7. Under this simulation condition, the in-plane temperature distribution at each time of each wafer that occurs transiently when the wafer row is inserted is described in IEICE Transactions (C) Volume 68 (1985), pages 425 to 432. Wafer temperature transient analysis model 3 shown in detail
And the result is written in the storage file 6. Furthermore, using this in-plane temperature calculation result, Proceeding of JSS ST International Conference Jurai (1986), pages 509 to 51 (Proc.JSST Int.Conf.July (1986) pp. 509-
In-plane thermal stress analysis model 4 detailed in 513)
The thermal stress corresponding to the slip system of the silicon crystal is calculated by and the result is written in the storage file 5. With the above processing, the numerical calculation by the simulation model calculation unit 1 for the set process conditions is completed, and the crystal defect of the crystal defect is evaluated by using the thermal stress evaluation graph as shown in FIG. 2 created on the screen of the graphic terminal 2. Proceed to occurrence evaluation. This graph shows a semi-logarithmic graph that gives a yield stress curve (σ _E (T)) 10 of a silicon material having a strong temperature dependence, and shows the rise of the wafer temperature of the thermal stress transiently generated when the wafer row is inserted. The accompanying changes are drawn as shown by curves 11 to 14 in FIG. 2 corresponding to the designated position in the wafer and the slip system by using the storage file containing the thermal stress calculation result. The results here are focused on the thermal stress generated at the peripheral portion of the diagonally upper portion of the central wafer in the 45 ° direction in which crystal defects are likely to occur. The thermal stress transition curve 12 shown in Fig. 2 is the case where the pipe wall temperature is lowered by 100 ° C compared to the curve 11, and the thermal stress transition curve 13 is the case where the wafer interval is doubled compared to the curve 11, and the thermal stress transition The curve 14 corresponds to the process condition when the specific wafer row insertion speed is 5 times that of the curve 13. From these results, the thermal stress transition curves 11 and 14 exceed the yield stress curve 10, and the thermal stress transition curves 12 and 13 do not exceed the yield stress curve 10. That is, it can be predicted that crystal defects will occur under the process conditions corresponding to the curves 11 and 14, and will not occur under the process conditions corresponding to the curves 12 and 13. Further, the sensitivity analysis of each process parameter such as the tube wall temperature, the wafer row insertion speed, and the wafer interval can be clearly understood as the relative positional relationship with the yield stress curve 10. Therefore, the above 3
This evaluation graph can be effectively used for problems such as how to set the other two parameters under the condition that one of the two process parameters is fixed and cannot be changed. For example, under the process conditions corresponding to the thermal stress transition curve 11 described above, it is predicted that the yield stress will be exceeded and crystal defects will occur, and the process conditions under which crystal defects do not occur are the constraint that the wafer row insertion speed is fixed. It is assumed that it is realized by the optimum combination of the other two parameters under. Here, the optimum means that the smaller the pipe wall temperature and the insertion temperature, and the larger the wafer interval, the more the thermal stress level is lowered. This means to consider this trade-off. Regarding the point that the decrease in the tube wall temperature lowers the throughput, in the current heat treatment process, the tube wall temperature is lowered by about 100 ° C from the processing temperature during the wafer row insertion to relax the thermal stress and finish the insertion. After that, a ramping method in which the temperature is raised to the processing temperature is adopted, which means that it takes a dead time to raise the temperature to the processing temperature by the amount of temperature decrease at the time of insertion. Now, returning to the above problem, in FIG. 2, when only the pipe wall temperature is changed with respect to the thermal stress transition curve 11 and the temperature is lowered by 100 ° C., the thermal stress level is as shown in the thermal stress transition curve 12, With respect to the yield stress curve 10, there is a large shift to the left, that is, to the safe side. On the other hand, when only the wafer interval is changed and doubled, the thermal stress level shifts downward with respect to the yield stress curve 10 as shown in the thermal stress transition curve 13, but the pipe wall temperature In comparison with the thermal stress transition curve 12 in which the temperature is decreased to the safe side, the yield stress curve 10 is approached particularly in the region where the wafer temperature is high. Considering the effect of the combination of these two process conditions on the throughput, the former requires the time required to raise the tube wall temperature by 100 ° C., and the latter requires half the number of processed batches. Furthermore, the tube wall temperature,
Even when both the wafer intervals are changed, the optimum process conditions can be rationally selected by proceeding on the thermal stress evaluation graph in the same manner. On the other hand, as another usage of the thermal stress evaluation graph,
There is an estimation of the yield stress curve of the target silicon wafer itself. It is expected that the wafer that flows through an actual semiconductor manufacturing line is subjected to repeated stress and thermal history in many heat treatment processes and the yield stress is reduced. The method of estimating the yield stress is shown in FIG. Thermal stress curve 21 in the figure
24 show the thermal stresses obtained by simulation corresponding to the process conditions in which the crystal defect generation evaluation experiment was conducted on a silicon wafer that had been subjected to a certain heat treatment in advance. (Curves 21, 22) and (Curves 23, 24) are obtained by setting two of the three process parameters under the same condition. Curves 21 and 22, and curves 23 and 24 correspond to the case where the remaining one process parameter is slightly changed. Now, assuming that a crystal defect occurs in the case of the process conditions of the thermal stress transition curves 21 and 23 and does not occur in the thermal stress transition curves 22 and 24, the yield stress curve of the wafer targeted here is a normal one. It can be estimated on this thermal stress evaluation graph that the yield stress of the silicon material is lower than the yield stress curve 10 and is given by the curve indicated by the broken line 20 passing between the curves 21 and 22, and between the curves 23 and 24. In addition, at the time of starting a new process such as increasing the diameter of a wafer, if there is no existing experimental data, the crystal defect generation data at the conventional wafer diameter is used, and the yield of the new process is as follows. If the stress curve is estimated, the number of experiments to find the process condition that suppresses the thermal stress within the thermal stress dislocation generation limit related to the heat treatment process at start-up can be greatly reduced, and a rational process supported by the physical model. Parameter optimization can be realized. For example, as the generation data of crystal defects in the conventional wafer diameter, the in-plane distribution is the region surrounded by the broken line in FIG.
If it exists like 30, the thermal stress transition curves 41 to 43 corresponding to the in-plane positions (α to γ) 31 to 33 marked with X in the figure are simulated as shown in FIG. The crystal defect generation data at each position, that is,
The yield stress curve 40 may be estimated on the thermal stress evaluation graph shown in FIG. 5 so that the crystal coincides with the boundary of occurrence of α, occurrence / non-occurrence of β, and no occurrence of γ. As in the above example, only the wafer diameter is increased, the manufacturing process specifications, and the strength characteristics of the unprocessed wafer, that is, the oxygen content, bulk defect density, substrate impurity type, etc., are the same when starting up a new process. Using the estimated yield stress curve, it is possible to predict whether or not crystal defects will occur in the wafer surface under the process parameters such as the wafer insertion speed in the heat treatment step of the present manufacturing process. For example, as shown in FIG.
When the tube wall temperature is fixed, it is possible to determine by simulation how wide the wafer interval is to prevent crystal defects from occurring. A simulation example of the wafer temperature transition is shown in FIG. This is a tube wall temperature of 950 ℃, insertion speed of 100cm / min,
A bird's-eye view of the temperature distribution 50 generated in the wafer surface at 1 minute and 30 seconds after the insertion of a φ150 mm wafer row with a wafer interval of 9.2 mm into the reaction tube is shown. Horizontal axes X and Y are wafer surface x
The distances in the axial direction and the y-axis direction are shown, and the vertical axis shows the wafer temperature. Further, the in-plane thermal stress model of the wafer can be constructed as follows. First, the wafer temperature changes dynamically from room temperature to about 1000 ° C during the insertion process and is dynamic, but does not show a sudden temperature change that indicates a thermal shock phenomenon. It is assumed that the in-plane temperature distribution that occurs every time is in a steady state. Further, since the wafer is an isotropic homogeneous elastic body and its thickness is sufficiently smaller than the radius of the wafer, as a plane stress problem when the above thermal load is applied,
The thermal stress {σ} = {σx, σy, τxy} is formulated by the finite element method using the triangular constant strain element. The matrix equation to be satisfied for each element is given by the following equation. [K] {δ} =-{F} _E0 (1) where [K] is the element stiffness matrix, {δ} is the displacement sequence vector, and {F} _E0 is the equivalent nodal force due to thermal strain acting on each node. Is a column vector of, and the initial strain due to the wafer temperature change amount ΔT from the reference temperature {E ₀ } = − {αΔT,
It is obtained from αΔT, 0}. α indicates a coefficient of thermal expansion. The wafer temperature of each element is the temperature T _wi , T _wj , obtained for each mesh intersection by the wafer temperature transient analysis model using the difference method, as shown in FIG.
The average value of T _wk was used. In addition, the temperature distribution within the wafer is y
Since it is symmetric with respect to the axis, as shown in FIG. 14, a half of the wafer plane with respect to the y axis was divided into finite elements and used as a calculation target. As a result, all the x-direction displacement u of the element contact points on the y-axis which is the target axis are 0, and the contact point between the wafer 141 and the boat 142 is the fixed point 143 in order to eliminate the rigid change in the y-direction. A boundary condition is assumed in which the y-direction displacement v is 0. Under this boundary condition, the simultaneous linear algebraic equations for unknown displacement, which are assembled for all elements by equation (1), are solved and the strain {ε} is calculated. The thermal stress {σ} for each element can be calculated from the linear relational expression. {Σ} = [D] ({ε}-{ε ₀ }) (2) Here, [D] represents an elastic stress-strain matrix including Young's modulus E and Boisson's ratio ν. In comparison with the yield stress, considering the slip surface {111} of the silicon wafer and the slip axis <110>, it corresponds to the five independent slip systems calculated from the thermal stress {σ} as follows. The decomposition shear stress | S ₁ | ~ | S ₅ | According to the above-described embodiment, the optimization of the wafer heat treatment process conditions can be realized on the computer by using the simulation model, so that the mass production line can be started in response to the increase in the diameter of the wafer or the change of the process specifications. Can be done quickly. The example of estimating the yield stress curve of the target wafer has been described above. Here, the determination method will be shown in more detail based on the empirical formula. Yield stress σ _E with temperature dependence of silicon wafer
The empirical formula of (T) is given as the formula (4). Where T is absolute temperature, k is Boltzmann's constant, U is activation energy related to slip motion of crystal, Is the strain rate, and n and C are experimental constants. Here, the uncertainties in which the yield stress itself changes for each target process specification due to the number of heat treatments mentioned above, the strength characteristics of the untreated wafer, etc.
Further strain rate It is necessary to reasonably explain the combination of. Strain rate Is equivalent to the time change rate of the thermal stress generated in the wafer surface from its physical meaning, and is the temperature rise rate of the wafer when the wafer row is inserted into the reaction tube, that is, one of the process parameters. Heavily dependent on speed. Therefore, it is a parameter that should be adjusted according to a large change in the insertion speed region, rather than a factor that causes the yield stress curve to vary depending on the number of heat treatments in the target process. Next, the characteristics of the yield stress curve when the experimental parameters n and C were changed are shown in FIGS. 7 and 8, respectively. In both figures, the yield stress curves 100 to 102 corresponding to three different manufacturing processes such as already estimated product targets and wafer substrate impurity types are also shown. The state of the yield stress curve corresponding to changes in n and C shown in FIGS. 7 and 8 is greatly different on this evaluation graph, and C dependence is higher than n dependence in the high temperature region. It has high sensitivity. That is, on the thermal stress evaluation graph given in semi-logarithm, the stress value taken on the vertical axis is, as is clear from the following equation (5), the change in C is only the parallel movement in the vertical direction, With respect to the change of n, according to the third term of the equation (5), the sensitivity of n becomes smaller as the wafer temperature T becomes higher. It can be seen that the changes in the yield stress curves 100 to 102 corresponding to the three types of target manufacturing processes described in FIGS. 7 and 8 can be well explained by FIG. 8, that is, the change in the experimental parameter C. The strain rate Was fixed at 0.25 × 10 ^-5 / sec in both figures. This value corresponds to the strain rate in the wafer row insertion rate region that is often used at present, as will be touched on by the effect of the strain rate on the yield stress described below. Finally, the strain rate I will touch on the effect of yield stress on yield stress. Strain rate Corresponds to the speed at which a load stress is applied, and as shown in the above empirical formula (1), this value causes the yield stress curve to fluctuate as shown in FIG. The yield stress value of the material by the usual tensile test clearly shows the order of this value. Now, the strain rate for the wafer when inserting the wafer row into the oxidation / diffusion device of interest here. Is largely dependent on the speed at which thermal stress transiently generated in the wafer surface is applied, that is, the wafer row insertion speed. The relationship between the wafer row insertion speed and the strain rate is shown in FIG. 10 using the wafer interval as a parameter. Here, the strain rate is calculated by the following equation, which is an equivalent side force due to temperature change during stress measurement by the finite element method, that is, initial strain ∈
Time change rate of ₀ Was represented by. Where t ₁ and t ₂ are times, and ∈ ₀₁ and ∈ ₀₂ are times t ₁
Represents the initial strain at and the initial strain at time t ₂ . As is clear from FIG. 10, the strain rate at the insertion speed of 50 cm / min or more is about 3 to 10 times higher than the strain rate at the insertion speed of 10 to 30 cm / min. As an example, for a φ150 wafer, the prediction evaluation of the occurrence of an absent crystal defect in consideration of the variation of the strain rate and the verification result by the experiment will be described below. FIG. 11 shows a thermal stress evaluation graph at this time. In the figure,
Thermal stress transition curve 110 has a low insertion rate and strain rate Corresponding to process conditions with It corresponds to. Further, the yield stress curve 112 is an already estimated one for the former strain rate region, and the yield stress curve 112 is
For 113, considering the change in strain rate under both conditions (3.3 times),
The yield stress curve modified for the latter crystal defect generation evaluation is shown. As is clear from this figure, in both conditions, if the already-estimated yield stress curve 112 is used as the boundary line of crystal defect generation,
The thermal stress transition curve 111 is much larger than the yield stress curve 112 than the thermal stress transition curve 110, and the latter should have more crystal defects than the former. However, in the experimental results, a clear slipline was observed at the local 45 ° direction of the wafer under the former process condition of low strain rate, but no slipline was observed under the latter process condition of high strain rate. Not done.
That is, no thermal stress dislocation was generated. This experimental fact can be well explained by evaluating the yield stress curve when the strain rate is high with the yield stress curve 113 increased by the increase. Therefore, be aware that the yield stress curve itself may increase under process conditions that significantly change the strain rate, such as a very high wafer row insertion rate. It is important to proceed with the evaluation. At that time, as described above, the change in the yield stress curve may be corrected by considering the change in the strain rate obtained from the equation (6) and modifying the yield stress σ _E (T) given by the equation (4). . [Advantages of the Invention] According to the present invention, in the heat treatment step of the semiconductor manufacturing process, the evaluation of the occurrence of crystal defects due to the thermal treatment that occurs when the wafer row is inserted into the oxidation / diffusion device is replaced by an experiment having a large manpower Since the physical model can be easily executed on a computer, there is an effect that the period can be greatly shortened such as the start-up of a new process accompanying the increase in the diameter of the wafer and the failure analysis for the process-induced defects.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a configuration diagram of an evaluation system when the present invention is realized on a computer, FIG. 2 is a diagram showing an example of a thermal stress evaluation graph for evaluating the occurrence of crystal defects, and FIG. Is a diagram showing an example of yield stress curve estimation, FIG. 4 is a wafer in-plane crystal defect generation distribution diagram, and FIG. 5 is a diagram showing an example yield stress curve estimation utilizing the in-plane distribution of crystal defects in FIG. , FIG. 6 is a wafer interval dependency diagram of thermal stress level, and FIGS. 7 to 9 are diagrams showing experimental constants n, C and strain rate dependency in the empirical formula of the yield stress curve, respectively, and FIG. Is a diagram of the relationship between the wafer row insertion speed and the strain rate, FIG. 11 is a diagram showing an example of crystal defect generation prediction evaluation in consideration of the strain rate dependence of the yield stress, FIG. 12 is the entire oxidation diffusion apparatus to which the present invention is applied. Fig. 13 shows the wafer temperature calculated by the wafer temperature transient analysis model. Shows a transition example, FIG. 14 is a diagram showing a finite element example against the wafer half due to thermal stress model in the wafer surface.

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Yoshihiko Kiyokuni               111 Nishiyokote-cho, Takasaki-shi Hitachi, Ltd.               Inside the Takasaki Factory (72) Inventor Fumio Wakamori               1099 Ozenji, Aso-ku, Kawasaki City Co., Ltd.               Hitachi Systems Development Laboratory (72) Inventor Akira Yoshinaka               1450 Kosui Honcho, Kodaira City Hitachi, Ltd.               Inside the Musashi Factory                (56) References IEICE Technical Report 84 [181               ] (1984) P. 1-8                 Junichi Nishizawa "Semiconductor Research 16"               (1979-8-15) Industrial Research Group P.               317-341

Claims (1)

(57) [Claims] In the high temperature processing step of the semiconductor manufacturing process, the transient characteristics of the in-wafer temperature distribution and the in-wafer thermal stress distribution characteristics are calculated by computer simulation based on a predetermined physical model, and the wafer surface relative to the wafer temperature is calculated based on the calculated characteristics. The thermal stress evaluation graph is created by drawing the transition curve showing the thermal stress transition and the yield stress curve of the wafer, and by estimating and estimating the above generation limit from the created graph, it is induced at the time of wafer row insertion / withdrawal. Wafer in-plane heat treatment, which comprises the process of predicting the occurrence of thermal stress dislocations based on the thermal stresses and the process of optimizing the process parameters of the heat treatment so as to keep the thermal stress within the predicted occurrence limits. Stress dislocation generation suppression method. 2. The physical model is a method for suppressing generation of thermal stress dislocations in a wafer according to the first term, which comprises a wafer temperature transient analysis model and a wafer thermal stress analysis model. 3. The method for suppressing generation of thermal stress dislocations in the wafer according to the first item, wherein the yield stress curve of the wafer itself of the target process is estimated on the evaluation graph by using already-existing data regarding the presence or absence of thermal stress dislocations.