JPS63145543A - Modulo-w circuit - Google Patents

Abstract

PURPOSE:To improve the overall trouble detecting rate and resolution ability of a check circuit by defining all wrong bits '1' as the modulo value when a trouble is detected. CONSTITUTION:A modulo-3 register 501 inputs 2-bit data D=[d1, d2] and a strobe signal STB and outputs 2-bit data E=[e1, e2]. For instance, if the STB is inputted with D=[0, 1] when the output E=[1, 0] is satisfied before input of the STB, the output E is changed to [0, 1] from [1, 0]. Under such conditions, if the STB is inputted with D=[0, 0] satisfied, the output E is changed to [0, 0] from [0, 1]. However the state [1, 1] is kept regardless of the value of D when the original state of the output E is equal to [1, 1]. Therefore the output E is fixed at [1, 1] after input of the STB if D=[1, 1] or E=[1, 1] is satisfied and a fact that a circuit preceding a modulo-W circuit has a trouble since [1, 1] shows originally the wrong data as the value of the modulo-3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device, and particularly to a modulo W circuit used for checking an arithmetic circuit or the like.

[Conventional technology]

The modulo W circuit is one of the check circuits that has been frequently used in the past mainly to check arithmetic circuits and the like.

Also, as the W of Moji and Las, W=2w-1 (for example,
3,7,15. ) is often used.

This is because the value of modulus and mouth W can be expressed by W pits, so it can be realized at a lower cost than other moduli.

Hereinafter, W=22-1=3 will be considered as a representative of W=2w-1. For the three values 0, 1.2 of modulo 3, 2
There are four values (0, 0
), (0,1), (1,0), and [1,1). For example, 0.0), 1
[0,1') for 2, and I:1.0) for 2.

FIG. 8 shows two sides of a conventionally used modulo three-channel circuit. In FIG. 8, when the arithmetic unit 9000 inputs the first human power data and the second human power data, the arithmetic unit 9000 stores them in the first human power data (land register 9001 and second human power data in the land register 9002,
1, the operation between the first manual operand and the second manual operand is executed, and the result is stored in the operation result register 9.
003 and then output.

Modulo 3 in this arithmetic device 9000.

The circuit is a modulo 3 expected value generation circuit 9012.

Consisting of a modulo 3 expected value register 9004, a modulo 3 matching checker circuit 9013, and an error display flag 9005, the mono/gut 3 expected value generation circuit 9012 is composed of a first manual operand register 9001 and a second manual operand register 9004. Operandre Nosta 9
When inputting the first human-powered operand and the second human-powered operand from 002 through the data inputs 901 and 902, the modulo 3 chain corresponding to the arithmetic circuit 9011 is executed, and the expectation of the modulo 3 of the arithmetic result is A value is generated and output to the modulo 3 expected value register 9004 through the data AS 912.

The modulo 3 expected value register 9004 inputs the modulo 3 expected value, which is the output of the modulo 3 expected value generation circuit 9012, through the data bus 912 and stores it.
Output to 3.

The modulo 3 match check circuit 9013 inputs the calculation result through the calculation result register 9003 and the data node 903, and also inputs the calculation result to the modulo 3 expected value register 900.
When the modulo 3 expected value is input through the data database 904 from 4, the calculation result modulo 3 is generated, and it is checked whether the value matches the modulo 3 expected value, and if they do not match. When the error report is sent to data bus 9
13 to the error display flag 9005.

The error display flag (hereinafter referred to as EIF) 9005 is.

When you enter an error report through the database 913,
Store it until you input the release signal from now on.

It retains its value and also sends error reports to the data 9 screen.
Output through 05.

Through the operations described above, a failure in the arithmetic unit 9000 is detected and reported, but in a typical modulo 3-chire circuit, the checks are executed in more detail than shown in FIG. is normal.

In other words, a similar matching check is performed not only on the final result of the arithmetic circuit but also on intermediate results. The modulo 3 expected value of the intermediate result in this case is input to the arithmetic circuit through the datax 921.

FIG. 9 is a diagram illustrating an example of a part of the arithmetic circuit in the arithmetic device, when performing mono, 3-check, and ri on the intermediate results.

In FIG. 9, the arithmetic circuit 5ooo receives two binary data X, Y and their respective modulo ternary values A, B, and
The calculation result 2 between binary data X and Y, the modulo 3 value C of the calculation result 2, and the error report E based on the result of the modulo 3 check are output.

1st manual register 81pl and 2nd manual register 802
After inputting and storing binary data X and Y, respectively,
Binary data X, respectively through data buses 81 and 82.
As shown in the figure, the binary data X and Y are input to the arithmetic circuit 811, and the binary data X and Y are input to the first person camodulo 3 generation circuit 812 and the second person camodulo 3 generation circuit 813, respectively. becomes.

When the arithmetic circuit 811 receives binary data X through the data bus 81 and binary data Y through the data bus 82, it executes an operation between the binary data X and Y, and sends the operation result 2 to the data bus 91. through the calculation result output register 8
Output to 03.

The calculation result output register 803 inputs and stores the calculation result 2 through the data/4' space 91, and then inputs and stores the calculation result 2 through the data/arm space 8.
The calculation result 2 is output through 3. The calculation result 2 becomes the output of the calculation circuit 8000.

It becomes an input to the calculation result modulo 3 generation circuit 816.

The first person Camodulo 3 generation circuit 812 is a data motherboard 8
When binary data X is input through 1, its modulo 3
A signal is generated and output through the data/gas 92, and the modulo 3 value is input to the matching circuit 814 and the first modulo 3 holding renostar 804.

The second person Camodulo 3 generation circuit 813 is a data/parameter 8
When binary data Y is input through 2, its modulo 3
A value is generated and output through the data signal 93, and the modulo 3 value is input to the match circuit 815 and the second modulo 3 holding register 8050.

The first modulo 3 holding renostar 804 and the second modulo 3 holding renostar 805 each input and store the modulo 3 values of binary data It is used as an input to the third calculation circuit 817.

The modulo 3 arithmetic circuit 817 inputs the modulo 3 value of the binary data X through the data bus 84 and the modulo 3 value of the binary data Y through the datax 85.
11 is executed, modulo 3 expected value of operation result 2 is generated, and outputted through data bus 97.

It is input to the matching circuit 818.

The calculation result modulo 3 generation circuit 816 is the data
When the operation result 2 is input through 3, a modulo 3 value of the operation result 2 is generated and input through the data 96 to the matching circuit 818 and the modulo 3 output register 806.

After inputting and storing the modulo 3 value of calculation result 2 through the data arm 96, the modulo 3 output renostar 806
7' - Modulo 3 value C of operation result 2 through tapas 86
Output. The modifier mouth 3 value C of calculation result 2 is calculated by calculation circuit 8.
It is used as an input to a subsequent modulo three-channel circuit (not shown) as one output of 000.

The matching circuit 814 inputs the modulo 3 value of the binary data X through the data bus 92, and also inputs the modulo 3 expected value A of the binary data
Check whether the value and its expected value A match,
If they do not match, an error report is output to an EIF (error display flag) 808 via the data bus 94.

Similarly, the matching circuit 815 compares the modulo 3 value of the binary data Y input from the data bus 93 with its expected value B, and sends the result to the EIF 809 via the data bus 95.
Output to.

Similarly, the matching circuit 818 compares the modulo ternary value of the operation result 2 manually input from the data bus 96 with the expected value input from the data bus 97, and outputs the result to the EIF 807 through the data bus 98.

When the EIFs 807, 808, and 809 receive an error report through the data/IP interface 98, 94.95, they store it, hold that value until a release signal is input, and then apply the value to the OR circuit. 810.

The OR circuit 810 includes EIFs 807, 808,
When an error report is input from any of the arithmetic circuits 809, an error report E indicating the occurrence of a failure is output as one output of the arithmetic circuit 8000.

[Problem that the invention seeks to solve]

In FIGS. 8 and 9, in the conventional modulo 3 circuit, modulo 3 is "the remainder when the numerical value indicated by the data is divided by 3.

'', the binary data (1, 1) is not considered as the value of monoyuro 3. However, modulo 3, which is originally used in data processing equipment,
The circuit is.

Since it is used in a check circuit to detect circuit failure, the value of modulo 3 changes due to a failure.
, 1] should also be considered.

For example, in FIG. 9, the first person Camodulo 3 generation circuit 8
12, the [111
) is output, the conventional mono.

The output for the input of the matching circuit 814.C1tl is undefined. The outputs of the mono/mouth 3 arithmetic circuit 817, the coincidence circuit 818, etc. have no logical meaning and depend on their circuit configurations.

Therefore, due to the failure of the modulo 3 circuit itself.

If a pattern of (1, 1) occurs, it is difficult to detect the failure, and even if the calculation result becomes incorrect due to a failure in the calculation circuit, the value of modulo 3 will be
If the output is the same as the output for (1, 1) above, the failure will not be detected, and the detection rate of the check circuit will drop significantly, and an error will be displayed in the check circuit below it. When the flag lights up, it becomes a factor that causes an error in pointing out the failure location.

In addition, when a part of the arithmetic circuit is realized by LSI etc., it is useful for evaluation to detect failure of the LSI etc. alone.

Normally, logic darts and logic patterns in LSI etc. are verified using the output of some kind of test node or turn input and the values in FRI, PROFLO, and f.

When a modulo 3 circuit is included in an LSI, the detection rate will not improve unless cases 1 and 13 are included as test inputs, so the arithmetic circuit as a whole is logically meaningless [1 , 1] is also required, and since the logic completely depends on the circuit configuration, the description becomes extremely complex and difficult to understand.

On the other hand, as a circuit using modulo 3.

As described above, the expected value of the object, mouth 3, and the value of modulo 3 generated from the actual calculation result are checked for consistency. Therefore, in order to limit the 1 detection rate.

It is necessary to generate expected values for each part of the arithmetic circuit and set error flags for each part, which requires a large increase in the amount of hardware, and when multiple error flags light up, it is possible that the cause is the same failure. It is difficult to determine whether the

In general, in conventional modulo W circuits, all bits @1' are not considered, so it is difficult to improve the fault detection rate 1 resolution as a monomodulo W circuit, and it is difficult to improve the fault detection rate as a monomodulo W circuit. When verifying a circuit, the disadvantage is that the meaningless logical description of all bits ``1#'' is an obstacle to improving design efficiency.In other words, the conventional modulo W circuit has the disadvantage that the meaningless logical description of all bits ``1#'' is an obstacle to improving design efficiency.

Although it is easy to design the circuit, Harity Che,
Compared to other checking and recirculating circuits, this method has the disadvantage that the detection rate when an error occurs and the resolution for pointing out the error location when detecting an error are low.

[Means for solving problems]

In the mono-W circuit of the present invention, all bits are “
The (W (=2''-1)) binary values excluding 1'' are defined as W codes modulo W.

All bits) @1' is a monoyuro W circuit defined as an error code indicating that a failure has occurred or that a failure has been detected, and n pieces of w bit data At.
"[al, a13e""*aty)+A2=("41
gIL! 2 e ””t atw:l l ””w
Ayl""('111 r "n2-...9a] is input, and the n inputs At e A2 *..., An
The result of the modulo W operation between W is D=(dl s dW
,...

dW], the input Al v kt 'e...
-, when one or more of An is (1-1?..., 1], C=[1, 1,..., 1]; otherwise, C=(ds + d2e") 'sdw), the W bit data D=(d
l, d, , ..., dw) and a strobe signal, and input the strobe signal with the output E = [1, 1, . ...,
l].

When a strobe signal is input in other conditions.

E==(dl m dW e ”” # dw )
The w bit data E=("1 * C2t ""
e@y), and when the modulo W value of the input/output or intermediate result of the modulo W operation is [1, 1, ..., 1], it is held and other At this time, the modulo W value is transmitted in synchronization with the strobe signal, the modulo W calculation is executed, and the calculation result is output.

In addition, the modulo W circuit of the present invention has the following characteristics:
Among the 2w binary values that can be expressed as , the binary values with all bits excluding "1"<W(=2"-1) are defined as W codes modulo W, All pits”
1” indicates that a failure has occurred.

Alternatively, it is a module W circuit defined as an error code indicating that a failure has been detected, and n W bit data AI = (all 5a12 e""t a1w
]#A2=C”21 e al2 p”@p azw
), 1l11+, A(1=(”n1#1n2.ms
, ILnw] as input, and the n inputs AltA2
The result of the mono-Yuro W operation between m ”” y An is D=
(dl e dW *””m dW), the input AleA2. ..., one or more of An is [1
, 1, -..., 1], then e C=(1v 1-...
・, 1], otherwise C=Cdl, dW +”
'e dy] W pi, data C; (C1sele
...”, ay] and the W bit data D” (dl + d2e ”” + dW
) and strobe signal as input, output E = (1,
1.

..., when a strobe signal is input in the state of 1).

E = [1, 1, ..., 1], if a strobe signal is input in any other state, e E = (dt e d2e...
, dW] is the w bit data ""("1 v C
2t ``” e @y), and the input D=(1, 1, ..., 1] or the output E=[1,
1, -, 1], when a strobe signal is input, f=1. Straw in other states! When a signal is input, modulo W outputs 1-bit data f where f = o.
When the input/output or intermediate result of the modulo W calculation is [1, 1, ..., 1],
It is configured to hold it, output an error report, and at other times transmit the mono-W value in synchronization with the strobe signal, execute the mono-W calculation, and output the calculation result. There is.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

In the following description, a case where W=3, that is, a modulo 3 circuit will be described.

FIG. 1 is a block diagram showing a first preferred embodiment of the present invention. In FIG. 1, the modulo 3 circuit 1000 has two modulo 3 values A=(al, 113].

B = [ble bz E is input, modulo 3 value A,
Executes mono, 3 operation between 8 and the result modulo 3
Output the value C=(el #ex).

The first input Kamoyuro 3 Renostar 101 is modulo 3 value A
=Cal g jL2] is input and stored by the strobe signal, and then the Cat*
a*) is output and input to the Mono-Yuro 3 arithmetic circuit 103. However, if the value stored in this register before the strobe signal was input was (1, 1), (4, t:l) would be held even after the strobe signal was input, and the input A would not be stored.

The second person camodulo 3 register 102 has a modulo 3 value B
”(bI e bz ) is input, and after being stored by the strobe signal, it is passed through the datax I2 and sent to [bI.

b2] and is used as another input of the modulo 3 arithmetic circuit 103. However, the value before strobe signal input is (1, 1
), [:1, 1] is held even after the strobe signal is input, and s (bI sb2 ) is not stored.

-11-Sh03 arithmetic circuit 103 inputs Cal+1L2) through data bus 11 and Cb+tbz and l through data bus 12, *l:"I, +
12] and [b1゜b2], and as a result, the modulo 3 value C=(at −c2:l
t data no J? The result is outputted through all the steps 13 and input to the calculation result modulo 3 renostar 104. However, data
When the modulo ternary value on the data bus 11 is (1, 1), or when the modulo ternary value on the data bus 12 is (1, 1).

The modulo 3 value output through Datax 13 is (
1,1).

The operation result modulo 3 register 104 is the data/base 1
After inputting (ct*cz) through the data bus 14 and storing it by the strobe signal, ""(et t
ex ] is output. This modulo 3 value C becomes the output of the modulo 3 circuit 1000. however.

When the value before strobe signal input is (1, 1).

(1, 1) is maintained even after the strobe signal is input.

C=(1,1) is output.

When (1,1) occurs on the modulo 3 data bus due to a failure in the modulo 3 circuit 1000.

The modulo ternary value (1,1) is transmitted to output C.

C=(1, 1) is output.

For example, if the output part of the first person's camodulo 3 register 101 fails and a modulo 3 value (1, 1) is generated on the data bus 11, the value of (1, 1) is transmitted through the modulo 3 arithmetic circuit 103. , passes through the datax 13, passes through the calculation result modulo 3 renostar 104, passes through the datax 14, and is output as C=[1, 1, 1. The value stored in the first human power Nananoyuro 3 register 101 and the second
Both the value stored in the manual 7-no-yuro 3 register are not [1, 1], but the operation result modulo 3 register 1
If the value held in 04 is (1, 1), it can be determined that the failure location is within the modulo 3 circuit 1000.

On the other hand, monoyuro 3 circuit 1ooo input B = (1, 1:1
In the case of , this modulo 3 value ["l, 1) is input to the second human-powered monoyuro 3 reno star 102 and stored, passes through the data path 12, and is sent to the data gas via the modulo 3 arithmetic circuit 103. 13, the calculation result is input to the modulo 3 renostar 104, stored, and then output through the data bus 14 as 5, C=(1,1).
The value stored in the Human Camodulo 3 register 101 is not [1,1].

The values held in the second person camodulo 3 register 102 and the calculation result modulo 3 register 104 are (1, 1
), the cause of the output C=(l, 13) is.

The second person's camouflage 3 is located in the circuit before the second person's camouflage 3 register 102 in the modulo 3 circuit 1000.
It can be determined that it is not between Renostar and Output C.

Figure 2 is a professional diagram showing the second embodiment of the present invention, and is an example of a combination of various arithmetic circuits equivalent to the 2113 circuit 1000 above in Figure 1, which is not a single operation but a more complex one. It constitutes a modulo 3 circuit for use in checking arithmetic circuits.

In the following description, 田 stands for mono so3 addition, 巹 stands for modulo 3 subtraction or inversion, and 口 stands for modulo 3 multiplication.

In FIG. 2, the upper 2113 circuit 2000 has six 2
For large inputs of base numbers X, Y, Z, R, S, To.

P=-(X0Y+Z-R), Q-=(X+Y-8-T)
-(x0Y+Z-R) corresponding to the arithmetic circuit that outputs the two binary numbers P and Q,
) respective modulo 3 values A, B, C, D, E.

Enter F, L = day (A field B field C day D), M = (A field B
Outputs two modulo 3 values, M, which are EEIF' ) El (AE8B, C, D).

Mono, mouth 3 circuit 2000 has 6 modulo 3 values A,
If you input B, C, D, E, F, modulo 3 values A, B
is sent to the modulo 3 addition circuit 201, and the modulo 3 values C and D are sent to the modulo 3 subtraction circuit 202.

The modulo 3 values E and F are distributed to the modulo 3 multiplication circuit 203 and used as respective inputs.

The modulo 3 addition circuit 201 outputs the mono 3 value A.

When B is input, a modulo 3 value indicating A and B is generated, outputted through the data bus 21, and sent to the modulo 3 adder circuit 204. It is assumed that the mono-Yuro 3 subtraction circuit 2050 is input.

The modulo 3 subtraction circuit 202 has a modulo 3 value C.

When D is input, a modulo 3 value representing the CEID is generated and output over the data bus 22 as another input to the modulo 3 adder circuit 204.

The SEF 103 multiplication circuit 203 is modulo 3-valued E.

When you input F, monoyuro 3 indicating EQF (=EXF)
generates a value and outputs it through the data bus 23.

This is another input of the mono/mouth 3 circuit 205.

Similarly, modulo-3 adder circuit 204. Modulo 3 subtraction circuit 205. The modulo 3 inversion circuit 206 and the modulo 3 multiplication circuit 207 are AEBB.

C[ID input A field B field C day, A field B.

E EI F input the A field B day EQF, A field B field C day input the day (A field B field C day D), A field B field C day, A field B3 EQF input Against.

(A, B, E[]F) (A, B, C3D) are generated and output through data nodes 24, 25, 26, and 27, respectively.

Due to the operation of each modulo 3 circuit described above, the modulo 3 circuit 2000 receives six inputs A, B, C, and D.

For E and F, L = day (A field B [EIC day D), M = (
AEBBEEEIF) mouth (Heda Bda C3D) 2
outputs the value M, modulo 3.

Here, when (1, 1) is generated as the value of mono, 3 in the modulo 3 circuit 2000 due to a failure in 2 circuits, or any of the 6 inputs A, B, C, D, E, F but〔
1, l] is input.

Either or both of the output values and M are output as [1, 1], and the modulo 3 register in the modulo 3 arithmetic circuit on the path taken by [1, 1] is (1, 1).
1) is maintained.

As a first example, if a failure occurs on the modulo 3 subtraction circuit 205 or the data bus 25 and (1, 1) is input to the modulo 3 multiplication circuit 207 through the data bus 25, the modulo 3 multiplication circuit 207 The output M is (1, 1) and 2M is invalid data.

It is clearly shown that a failure has occurred somewhere up to M.

As a second example, if the input is input as invalid data (1, 1), the output of the modulo 3 subtraction circuit 202 passes through the data bus 22, and from the modulo 3 addition circuit 204 through the data bus 24. 3. Output from the inverting circuit 206 through the data bus 26 and the multiplication circuit 2 of the SEFF 103.
Both outputs M from 07 through data bus 27 are (1,
It becomes 13.

L and M are invalid data, which clearly indicates that a failure has occurred somewhere between L and M.

In the case of the conventional modulo 3 circuit, since no consideration is given to invalid data (1, 1), the above-mentioned first . When a failure like the one in the second example occurs, the values of L and M depend on other inputs and circuit configurations, so it is difficult to determine whether or not the data is invalid, and there are cases where it is not detected. come.

Furthermore, when pointing out a failure location, it is difficult to judge the value of incorrect data in the middle, so the resolution becomes extremely low.

On the other hand, in the case of the 9th embodiment, invalid data can be easily determined by the value (1, 1), so the failure detection rate is high, and the value of the path through which the value (1, 1:] passes is All (1,1)
Since it is held, it is easy to find the fault that causes the value of (1, 1), and the 2-resolution is also high.

Also, unlike the conventional modulo 3 circuit, the input is [1,
1], and the outputs [1, 1, 1 are also logically meaningful values. For example, if the modulo 3 circuit 2000 is
If realized using SI, etc., there will be no cases that were not taken into account when designing the 9 circuits during logic verification, and LS
There is no need for extra labor just for logic verification of a single unit such as I, and it does not interfere with design efficiency.

FIG. 3 is a diagram showing a third embodiment of the present invention, and the three modulo 3 registers in the modulo 3 arithmetic circuit 1000 shown in FIG. When a strobe signal is input in the state of (1, 1), f=1. This is an example equipped with a modulo 3 register which has the added function of outputting 1-bit data f where f=o when a strobe signal is input in any other state.

In FIG. 3, the first Camodulo 3 reno star 301 inputs A'' (al*a2), stores it by a strobe signal, and then outputs (al
. When you enter .

If a strobe signal is input when f, = l, or in any other state, f1 = 0, and outputs data fl.
fl""When it becomes 1, there are 2 lines, and in the nosta there is (1, 1:
The value of l is held and does not change regardless of the input of the strobe signal.

7g2 person camodulo 3 register 302 is B=[bI,
b2] is input and stored by the strobe signal,
Output (bl, bz) through the data bus 32,
In addition to using it as another input of the mono/mouth 3 calculation circuit 303, if the strobe signal is input when input B is [1, 1] or when the held value before strobe input is (1, 1), When a strobe signal is input in other states such as f,=:l, it outputs 1-bit data f2 in which f2=0.

When f2=1, the value (1, 1) is held in the nostar and does not change regardless of the input of the strobe signal.

Since the modulo 3 arithmetic circuit 303 is equivalent to the modulo 3 arithmetic circuit 303 in FIG. 1, a description thereof will be omitted.

The operation result modulo 3 register 304 is the data file 9
The modulo ternary value of the result of the operation modulo through 3 (cte
es) is input, and after being stored by the strobe signal, C"(e1# at) is output through the data node 34, and if the input (eteez) is (1, 1),
Or, if the strobe signal is input when the held value before the strobe input is (1, 1).

f3=1. In other states, when a strobe signal is input, f3=0 and outputs data f3,
When f3 = 1, there is one line and there is (1, 1:
The value of l is held and does not change regardless of the input of the strobe signal.

Due to the above operation, the modulo 3 circuit 3000.

2 modulo ternary A”(at * a2) * B=
Cbt t bl ] as input and performs modulo 3 operation between A and 8.

The resulting modulo 3 value C=(et e e2 :l is output, and due to a failure in the modulo 3 circuit 3000.

If (1,1) occurs on the modulo 3 data bus, input A is [1,1], or input B is (1,1).
), its modulo 3 value is transmitted to the output C, and C
= [1,l] is output, (1,1) is held in the modulo 3 register on the (1,1:1 transmission path, and fief! or f3 becomes 1 and is output.

Moreover, the modulo 3 circuit 3000 is also the modulo 3 circuit 3000 shown in FIG.
Similar to the circuit 1000, by configuring a plurality of circuits in multiple stages, a modulo-three circuit for use in checking a more complicated arithmetic circuit, such as the modulo-three circuit 2000 in FIG. 2, can be constructed. I can do things.

FIG. 4 shows a fourth embodiment of the present invention.

This is a diagram showing three 1-bit data flHf2ef3 output from the modulo 3 arithmetic circuit 3000 in FIG.
This is an example in which a circuit that generates the logical sum E of is added.

In FIG. 4, the first person Camodulo 3 register 401,
2nd person Camodulo 3 register 402. Modulo 3 arithmetic circuit 403. The calculation result modulo 3 register 404 is the first person's camodulo 3 register 301 and the second person's camodulo 3 register 3 in the modulo 3 circuit 3000 in FIG.
02. Modulo 3 arithmetic circuit 303. Operation result modulo 3
Since it is equivalent to the register 304, the explanation will be omitted.

The OR circuit 405 is the first Camodulo 3 register 40.
1, the output f2 of the second person's camodulo 3 register 402, and the output f3 of the calculation result modulo 3 register 404.
Generate and output.

fl *f2 pf3 is the respective modulo 3
When the value held in the register is [1, 1], that is, it is 1 pin data that becomes 1 when a failure is detected, so the logical sum E = 1 indicates that a failure has been detected in the modulo 3 circuit 4000. will be shown.

Due to the above operation, the modulo 3 circuit 4000.

2 modulo ternary values A” (iLl + lL2]r
Take B=(bI t b2) as input and perform modulo 3 operation between A and B.

The resulting modulo 3 value C = CcI * ez) is output, and if (1, 1) occurs on the data surface of modulo 3 due to a failure, the output C = (1, 1)
is output, (1, 1) is held in the modulo 3 register on the transmission path, and 1-pit data E=1 indicating failure detection is output.

In addition, the modulo 3 circuit of Figs. 1 and 3 is 1000°30
Similar to 00, by having a plurality of units and multiple stages, it is possible to configure a MOJI 303 circuit for use in checking a more complicated arithmetic circuit.

FIG. 5 is a truth table showing an example of a modulo 3 arithmetic circuit used in the present invention. (,) is an addition circuit.

(b) corresponds to a subtraction circuit, (C) corresponds to a multiplication circuit, and (d) corresponds to an inversion circuit. These are truth tables for modulo 3 addition, modulo 3 subtraction, monodulo 3 multiplication, and modulo 3 inversion circuits, respectively. - in the figure indicates an arbitrary value.

An example of an adder circuit (,) will be explained. In an adder circuit that calculates the sum 2 of arbitrary two binary numbers X and Y, the modulo 3 value of the input binary number
? 112] lThe modulo 3 value of the input binary number Y is B=
[b, #b2], the addition result of binary numbers X and Y is 2
Expected value C=(cl+cz:l) as the modulo 3 value of
Prepare. For example, A=(:0.1).

When B=(1,0), from the truth table of (,), C=(0,
0).

The above is equivalent to the conventional modulo 3 circuit.

The feature of this circuit is that [1,1:1] is considered as the value of modulo 3. If, from binary number X, mozoyu03 O
If A = [1, 1] due to a failure in the circuit that generates the value A = (at e &2), 9 expected value C = [ci, cz] = as shown in the truth table in (a). [1, 1] The same applies to the failure on the binary Y side.

In other words, there are three cases in which the expected value C is (1, 1), one is when A = (1, 1), and the other is when B = (1,
1:I, and a case where C=(1,1) due to a failure of the modulo 3 addition circuit itself.

FIG. 6 is a truth table and (b) a diagram showing an example of a modulo 3 register used in the present invention.

In FIG. 6, the modulo 3 register 501 has two pins, data D=(d, , d2:] and strobe signal ST.
With B as input, (a) With the logical configuration shown in the truth table,
2-bit data E"" (lltrex) is output.

For example, when the output E = (1,0) before the strobe input, when the strobe signal is input at D = [0,l), the output E changes from (1,03 to (:0.1)). do.

Similarly, in this state, if a strobe signal is input with D=(0,0), the output E will change from (0,13 to (0,0)
Changes to However, when the original state of the output E is (1, 1), the state of [1, 1] will be maintained regardless of the value of D. Therefore, when D = (1, 1) or E = (1, 1), the output E after strobe input is fixed at (1, 1) and 9
Since (1, 1) is originally invalid data as a value of modulo 3, it means that a failure has occurred in the circuit before the first circuit. Furthermore, if an error report signal is generated from the invalid data (1, D) of this circuit, this circuit will also serve as an error display flag.

FIG. 7 shows an example of a modulo 3 renostar in which a function is added to the modulo 3 register 501 in FIG. 6 to output bit data f that can be used for error reporting, etc.
It is a truth table and (b) a diagram.

In FIG. 7, modulo 3 register 502 is.

Input the 2-pin data D=(dl, d, ) and the strobe signal STB, and use the logic configuration shown in the truth table (a) to trigger the 2-pin trigger. E" (al # ez '3, 1 pin, and data f are output. 1 pin and data f are
When the strobe signal is input in the state where the input D=(1, 1), it becomes 1, and thereafter the state of f=1 is maintained with the output E=(1, 1). This 1 pin, data f
=1 means that invalid data (1, 1) has been input, so it can be used as is as an error report signal. The other operations are the same as those of the modulo 3/zostar 501 described in FIG. 6, so the explanation will be omitted.

In addition, although the above-mentioned embodiment describes a modulo 3 circuit, the present invention is not limited to this.

Of course, the present invention can also be applied to a mono-YuroW (=2w-1) circuit.

〔Effect of the invention〕

As explained above, the present invention takes into account all bits "'1" (error code) which are invalid as the value of Monoyuro W, and checks by setting the error code to the value of Modulus W at the time of failure detection. Not only can faults in the error code of the circuit itself be detected, but also the fault detection of the fault in the previous stage can be transmitted to the check circuit in the later stage.Furthermore, by tracing the transmission path of the error code, it is easy to determine the location of the fault.
This has the effect of improving the failure detection rate per resolution of the entire circuit, and also making it suitable for LSI implementation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment of the present invention;
The figure is a diagram showing a second embodiment in which a plurality of various modulo-3 circuits equivalent to the modulo-3 circuit in Fig. 1 are used in multiple stages, and Fig. 3 is the first embodiment in Fig. 1. FIG. 4 is a block diagram showing a third embodiment in which functions are added to the third embodiment shown in FIG.
diagram. FIG. 5 is a truth table showing an example of a modulo 3 arithmetic circuit used in the present invention, and FIG. 6 is a truth table showing an example of a modulo 3 arithmetic circuit used in the present invention.
A truth table and a diagram showing an example of a register, Figure 7 is a modulo 3 register with added functionality to the modulo 3 register in Figure 6.
A truth table and a block diagram showing an example of a renostar, and FIG. 8 is a block diagram showing an example of a conventionally used modulo 3 circuit. FIG. 9 is a diagram showing an example of a modulo 3 circuit for intermediate results, which is part of the arithmetic circuit in the arithmetic device. 101.102,104,301,302゜304.4
01,402,404,501,502...mono, mouth 3 renostar, 103,303,403...moji, mouth 3 calculation circuit, 1000,2000.3000°4000...
・Modulo 3 circuit, 201.204...Modulo 3 addition circuit, 202,205...Modulo 3 subtraction circuit, 2
03.207... Modulo 3 multiplication circuit. 206...modulo 3 inversion circuit. Fig. 5 (cL) (b) (C) ((2') Fig. 6 (α) (b) Fig. 7 (α) (b) Fig. 8 Akira 1 person Ka data Earth 2 person Kaa.

Claims (1)

[Claims] 1. Out of 2^w binary values that can be expressed with w bits (w≧2), W (=2^w) in which all bits exclude “1”
w-1) binary values are defined as W codes modulo W, and all bits “1” are defined as error codes indicating that a fault has occurred or a fault has been detected. A modulo W circuit with n pieces of w-bit data A_1=[a_1_1, a_1_2, . . .
, a_1_w], A_2=[a_2_1, a_2_2,
..., a_2_w], ..., A_n=[a_n_1
, a_n_2, ..., a_n_w] as input, and the n
D = [d_1, d_2, ..., d_
w], the inputs A_1, A_2, ..., A
When one or more of _n is [1, 1, ..., 1], C=[1, 1, ..., 1], otherwise C=
A modulo W arithmetic circuit that outputs w-bit data C = [c_1, c_2, ..., c_w] that becomes [d_1, d_2, ..., d_w], and w-bit data D = [d_1].
, d_2, ..., d_w] and a strobe signal, and input the strobe signal with the output E = [1, 1, ..., 1], E = [1, 1, ... ,1],
If a strobe signal is input in any other state, E=[d
_1, d_2, ..., d_w] and a modulo W register that outputs w bit data E = [e_1, e_2, ..., e_w]. W value is [1, 1, ..., 1]
1. A modulo W circuit that holds the value when , and transmits a modulo W value in synchronization with a strobe signal at other times, executes a modulo W calculation, and outputs the calculation result. 2. Among the 2^w binary values that can be expressed with w bits (w≧2), all bits are W (=2^
w-1) binary values are defined as W codes modulo W, and all bits “1” are defined as error codes indicating that a fault has occurred or a fault has been detected. A modulo W circuit with n pieces of w-bit data A_1=[a_1_1, a_1_2, . . .
, a_1_w], A_2=[a_2_1, a_2_2,
..., a_2_w], ..., A_n=[a_n_1
, a_n_2, ..., a_n_w] as input, and the n
D = [d_1, d_2, ..., d_
w], the inputs A_1, A_2, ..., A
When one or more of __n is [1, 1, ..., 1], C=[1, 1, ..., 1], otherwise C=
A modulo W arithmetic circuit that outputs w-bit data C = [c_1, c_2, ..., c_w] that becomes [d_1, d_2, ..., d_w], and w-bit data D = [d_1].
, d_2, ..., d_w] and a strobe signal, and when the strobe signal is input with the output E = [1, 1, ..., 1], E = [1, 1, ... ,1],
If a strobe signal is input in any other state, E=[d
w-bit data E = [e_1, e_2, ..., e_w] which becomes [_1, d_2, ..., d_w], and the input D = [1, 1, ..., 1] or the output Modulo W that outputs 1-bit data f when a strobe signal is input in a state where E = [1, 1, ..., 1], f = 1, and f = 0 when a strobe signal is input in any other state. Equipped with a register, the modulo W value of the input/output or intermediate result of the modulo W operation is [1, 1, ..., 1]
When , it holds it and outputs an error report, and at other times, it transmits the modulo W value in synchronization with the strobe signal, executes the modulo W calculation, and outputs the calculation result. Modulo W circuit.