JPS6314532A - Frame aligner circuit - Google Patents

Abstract

PURPOSE:To use only one elastic memory circuit required for the titled frame aligner circuit by adopting the constitution in which the phase in the circuitry is controlled by the phase of a transmission line. CONSTITUTION:A tank circuit 1 extracts a clock signal 21 from a transmission signal 20 and it is sent to an identification circuit 2, a frame synchronizing circuit 3 and an elastic memory circuit 4. The circuit 2 receives the signal 21 to identify the signal 20 and converts it into a device signal 22 and gives the result to the circuits 3, 4. The circuit 3 applies frame synchronizing processing and sends control signals 23, 24 to the circuit 4 and a frequency division circuit 9 respectively. An oslillation circuit 6 generates an internal clock signal 25 of the same frequency as that of the signal 21 and sends it to a selection circuit 7. A selection control circuit 37 outputs a control signal 30 being the result of detecting an L level of the signal 21, the circuit 7 selects a signal 25 or 21 depending on the L/H level of the signal 21 and sends a clock signal 26 to the circuit 9. The circuit 9 outputs a frequency division signal 28 of the signal 26 to allow a decoder 8 to send a frame signal 31 and a control signal 27. The circuit 4 writes a signal 22 according to the signals 21, 23 and read and output the data 29 according to the signals 26, 27.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a frame aligner circuit included in a digital exchange or the like.

2. Description of the Related Art A frame aligner circuit included in a conventional digital switching system has two elastic memory circuits as shown in FIG. Hereinafter, the circuit operation will be explained according to FIGS. 3 and 4. A transmission signal 20 from a transmission path or another device is input to a tank circuit 1 and an identification circuit 2. Tank circuit 1 extracts only the clock component of the transmission signal 20 as a clock signal 21, and then outputs it to an identification circuit 2 and a frame. It is sent to the synchronization circuit 3 and the elastake memory circuits 4 and 10. The identification circuit 2 identifies the transmission signal 20 using the clock signal 21 from the tank circuit 1, converts it into an internal device signal of TTL level, for example, and sends it to the frame synchronization circuit 3 and the erasure memory circuits 4 and 10. In the frame synchronization circuit 3, the signal 22 from the identification circuit 2 and the tank circuit 1
It performs frame synchronization with the original clock signal 21, recognizes the frame position of the signal 22, and sends control signals 23 and 24 to the erasure memory circuit 4, 1o1 comparison circuit 5, and latch circuit 11, respectively. The voltage control oscillator 6 generates a clock signal 25 in accordance with the DC voltage signal 26 from the integrating circuit 12 and sends it to the counter circuit 9 and the elastake memory circuits 4 and 10. The counter circuit 9 divides the frequency of the clock signal 25 from the voltage control oscillator 6 and sends an address signal 28 to the decoder circuit 8. In the decoder circuit 8, the address signal 28 from the counter circuit 9
is decoded to generate control signals 27, 32, and 30, which are sent to the elastake memory circuit 4, the elastake memory circuit 10, the comparator circuit 5, and the latch circuit 11, respectively. The latch circuit 11 receives the control signal 3 from the decoder circuit 8.
0 and the signal 24 from the frame synchronization circuit 3, a latch operation is performed and a control signal 35 is sent to the integration circuit 12. The output circuit 12 integrates the signal 35 from the latch circuit 11, converts it into a DC voltage signal, and sends it to the voltage control oscillator 6. When the phase of the signal 30 from the decoder circuit 8 is delayed with respect to the signal 24 from the frame synchronization circuit 3, the DC voltage of the signal 26 from the integrating circuit 12 increases the oscillation frequency of the voltage controlled oscillator 6. rise to Also, the decoder circuit 8 receives the signal 24 from the frame synchronization circuit 3.
If the phase of the signal 30 from
The DC voltage of the signal 26 from the voltage control oscillator 6 decreases so that the oscillation frequency of the voltage controlled oscillator 6 becomes lower. The error take memory circuit 4 converts the signal 22 from the identification circuit 2 into a control signal 21.
23, write to internal memory according to control signal 25.
Readout is performed according to 27. The elastake memory circuit 10 converts the signal 22 from the identification circuit 2 into a control signal 21.
23, write to internal memory according to control signal 25.
Readout is performed in accordance with No. 32. The comparison circuit 5 compares the phases of the control signals 23, 32, and 27 and generates a control signal 36. The control signal 36 takes a value such that when the phase difference between the control signals 23 and 27 is larger than the phase difference between the control signals 23 and 32, the selection circuit 7 selects the output signal 34 from the elastake memory circuit 4, Further, when the phase difference between the control signals 23 and 27 is smaller than the phase difference between the control signals 23 and 32, the selection circuit 7 takes a value such that the output signal 33 from the elastake memory circuit 10 is selected.
It is output as a data signal 29.

Then, the above-mentioned clock signal 25. The data signal 29 and the frame signal output from the decoder 8 are supplied to circuits after this circuit, for example, each circuit in a digital exchange.

Problems to be Solved by the Invention However, the conventional frame aligner circuit as described above requires two elastake memory circuits, which increases the mounting area and complicates control.

Means for Solving the Problem 1: The device is configured so that the phase within the device is controlled by the phase of the transmission line.

Function The elastic memory circuit required in the frame aligner circuit is reduced to one circuit.

Embodiment A frame aligner circuit according to an embodiment of the present invention will be explained below.

FIG. 1 shows a 7-frame aligner circuit according to an embodiment, and its circuit configuration includes a conventional circuit (see FIG. 3), a comparison circuit 5, an elastic memory circuit 10. The latch circuit 11 and the integration circuit 12 are excluded, and a selection control circuit 37 is added.

The circuit operation will be explained below with reference to FIGS. 1 and 2. A transmission signal 20 from a transmission path or another device is input to a tank circuit 1 and an identification circuit 2, and the tank circuit 1 extracts a clock component of the transmission signal 20 and outputs it as a clock signal 21 to an identification circuit 2 and a frame synchronization circuit 3. , is sent to the elastake memory circuit 4. In the identification circuit 2, the transmission signal 2
0 is identified using the clock signal 21 from the tank circuit 1, converted into, for example, a TTL leveling device internal signal, and sent to the frame synchronization circuit 3 and the elastake memory circuit 4. The frame synchronization circuit 3 performs frame synchronization processing based on the signal 22 from the identification circuit 2 and the clock signal 21 from the tank circuit 1, recognizes the frame position of the signal 20, and sends the control signals 23 and 24 to the elastake memory circuit 4, respectively. It is sent to the circulation circuit 9. In the transmitting circuit 6, the clock signal 21
The selection circuit 7 generates an internal clock signal with the same frequency as
Send to. The selection control circuit 37 detects the low level (hereinafter referred to as "L") of the clock signal 21 and selects the selection circuit 7.
When the clock signal 21 is "L", the control signal 30 is sent to select the internal clock signal 25, and when the clock signal 21 is high level, the control signal 30 is sent to select the internal clock signal 25.
A control signal 30 is sent to select the . Selection circuit 7
Then, select either the clock signal 21 or the internal clock signal 25 according to the signal 30 from the selection control circuit 37,
The new lock signal 26 is sent to the frequency dividing circuit 9.

The frequency dividing circuit 9 divides the frequency of the clock signal 26 from the selection circuit and outputs a control signal 28 to the decoder 8. Decoder 8
Then, according to the input, the control signal 27 and the frame signal 3 are
Sends 1. In the erasure take memory circuit 4, the signal 22 from the identification circuit 2 is written into the internal memory according to the control signals 21 and 23, read out according to the control signals 26 and 27, and a data signal 29 is sent out.

Effects of the Invention Since only one elastic memory circuit is required in the frame aligner circuit, control can be simplified and the mounting area can be smaller than in the past.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a 7-frame aligner according to an embodiment of the present invention, FIG. 2 is a time chart showing the operation timing of each part in the same embodiment, and FIG. 3 is a diagram showing the configuration of a conventional frame aligner. The block diagram and FIG. 4 are time charts showing the operation timing of each part in the conventional example. 1...Tank circuit 2...Identification circuit 3.
... Frame synchronization circuit 4.10 ... Erastake memory circuit 5 ...
Control circuit 6... Sending circuit 7... Selection circuit 8... Decoder circuit 9... Counter circuit 37... Selection control circuit Name of agent Patent attorney Toshio Nakao and 1 other person Figure 1 Figure 2 Figure 2f q Figure 3

Claims (1)

[Claims] a tank circuit that receives a signal from a transmission line and extracts a clock signal; an identification circuit that receives a clock signal from the tank circuit and a signal from the transmission line and converts a transmission line code into an internal signal; a frame synchronization circuit that receives a signal from an identification circuit and a clock signal from the tank circuit and performs frame synchronization processing; a selection control circuit that detects a low level of the clock signal from the tank circuit and generates a switching signal; an oscillator that generates a clock signal different from the clock signal; and a oscillator that receives a clock signal from the oscillator and a clock signal from the tank circuit, and generates the two clock signals by a signal output from the selection control circuit. a selection circuit that selects a clock signal, a counter circuit that receives and divides the clock signal output from the selection circuit, a decode circuit that decodes the signal from the counter circuit, and a signal from the identification circuit that outputs the signal from the tank circuit. Writing to an internal memory according to a clock signal from the frame synchronization circuit and a signal from the frame synchronization circuit, and according to a clock signal from the selection circuit and a signal from the decoding circuit,
A frame aligner circuit characterized by having an elastic memory circuit that reads internal memory.