JPS6314520Y2 - - Google Patents
Info
- Publication number
- JPS6314520Y2 JPS6314520Y2 JP16700181U JP16700181U JPS6314520Y2 JP S6314520 Y2 JPS6314520 Y2 JP S6314520Y2 JP 16700181 U JP16700181 U JP 16700181U JP 16700181 U JP16700181 U JP 16700181U JP S6314520 Y2 JPS6314520 Y2 JP S6314520Y2
- Authority
- JP
- Japan
- Prior art keywords
- line
- parallel
- parallel lines
- wave trap
- ferrite magnetic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 229910000859 α-Fe Inorganic materials 0.000 claims description 10
- 239000003990 capacitor Substances 0.000 claims description 6
- 238000004804 winding Methods 0.000 claims description 3
- 239000004020 conductor Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 238000003780 insertion Methods 0.000 description 3
- 230000037431 insertion Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Filters And Equalizers (AREA)
- Noise Elimination (AREA)
Description
【考案の詳細な説明】
本考案は２本の平行線路の各々の線を筒状フエ
ライト磁心の中心の孔の中を通し、さらにその両
筒状フエライト磁心の中心孔内に共通に導体を多
数回巻線を行ない、その巻線をコンデンサの両端
子に終端した平衡型のウエーブトラツプである。[Detailed description of the invention] This invention passes each line of two parallel lines through a hole in the center of a cylindrical ferrite magnetic core, and further includes a number of common conductors in the center hole of both cylindrical ferrite magnetic cores. This is a balanced wave trap with a round winding and the windings terminated at both terminals of a capacitor.
従来第１図に示すように受信機のアンテナ線回
路のような２本の平行線路において、受信を希望
しない雑音となるような不必要な信号成分を除去
する目的で、ウエーブトラツプが用いられてい
る。このウエーブトラツプは第１図ａのように平
行線路８，８′の一方の線路８の途中にインダク
タンス１とキヤパシタンス２の並列回路、または
第１図ｂのようにインダクタンス１とキヤパシタ
ンス２の直列回路の共振回路を挿入して、不必要
信号成分に共振させて除去する。また第１図ｃの
ようにインダクタンス１、キヤパシタンス２から
なる並列共振回路を平行線路８中に、またインダ
クタンス１′、キヤパシタンス２′からなる直列回
路を両平行線路８，８′の間に挿入することも行
なわれてきた。しかしこれらの方法は既設の線路
に対しては第１図ｃに示すように線路の途中を切
断点３で切断した後、ウエーブトラツプを挿入し
なければならず、既設の線路においては作業が複
雑で、線路が高圧線路の場合は挿入作業に危険が
伴う欠点がある。また除去しなければならない挿
入位置を線路の中から探し出す困難がある。 Conventionally, as shown in Figure 1, wave traps have been used in two parallel lines, such as the antenna line circuit of a receiver, to remove unnecessary signal components such as noise that is not desired to be received. ing. This wave trap consists of a parallel circuit of inductance 1 and capacitance 2 in the middle of one of the parallel lines 8 and 8' as shown in Fig. 1a, or a series circuit of inductance 1 and capacitance 2 as shown in Fig. 1b. A resonant circuit is inserted into the circuit to resonate and eliminate unnecessary signal components. Also, as shown in Figure 1c, a parallel resonant circuit consisting of an inductance 1 and a capacitance 2 is inserted into the parallel line 8, and a series circuit consisting of an inductance 1' and a capacitance 2' is inserted between both parallel lines 8 and 8'. This has also been done. However, with these methods, as shown in Figure 1c, it is necessary to cut the line midway at cutting point 3 and then insert a wave trap. The disadvantage is that it is complicated and the insertion work can be dangerous if the line is a high-voltage line. There is also the difficulty of finding the insertion position within the track that needs to be removed.
本考案は従来のかかる欠点を除き平行線路にそ
れぞれフエライト磁心を取り付けて、その間を導
体で巻回を施して線路を切断することなく安全に
作業のできる平衡型ウエーブトラツプを提供す
る。 The present invention eliminates such drawbacks of the conventional method and provides a balanced wave trap in which a ferrite magnetic core is attached to each parallel line, and a conductor is wound between the parallel lines so that the work can be carried out safely without cutting the line.
本考案は第２図の実施例に示すように、平行線
路８，８′のそれぞれを筒状フエライト磁心６，
６の中心孔９に通し、そのフエライト磁心６，
６′の中心孔９の中を通して共通に複数回の導体
７を巻回し、その終端をコンデンサ５で接続す
る。このようにして組立てられたウエーブトラツ
プの等価回路は、第３図に示すように平行線路
８，８′と磁気的に結合されたコイル４，４′をコ
ンデンサ５で終端した形となる。これによつて平
行線路８，８′の端子間のインピーダンスを下げ、
コイル４，４′のインダクタンス値とコンデンサ
５の容量とによつて設定された周波数を除去する
ことができる。 In the present invention, as shown in the embodiment of FIG.
6 through the center hole 9 of the ferrite magnetic core 6,
A conductor 7 is commonly wound a plurality of times through the center hole 9 of 6', and the ends thereof are connected with a capacitor 5. The equivalent circuit of the wave trap thus assembled has a configuration in which coils 4, 4' are magnetically coupled to parallel lines 8, 8' and terminated with a capacitor 5, as shown in FIG. This lowers the impedance between the terminals of parallel lines 8 and 8',
The frequency set by the inductance value of the coils 4, 4' and the capacitance of the capacitor 5 can be removed.
したがつて本考案のウエーブトラツプを使うこ
とにより、良好な特性を得ることができ高圧線路
でも安全に作業ができ、且つ挿入位置は平行線路
８，８′上をフエライト磁心６，６′を導体７とと
もに移動し、雑音の遮蔽効果の最適な位置を探し
出すことは容易である。なお本考案における筒状
フエライト磁心６は平行線路８に挿入できるよう
に２個の割型とすれば既設の線路でも線路を切断
することなく取り付けることができる。 Therefore, by using the wave trap of the present invention, it is possible to obtain good characteristics and work safely on high voltage lines, and the insertion position is such that the ferrite cores 6, 6' are inserted on the parallel lines 8, 8'. It is easy to move along with the conductor 7 and find the optimum position for the noise shielding effect. If the cylindrical ferrite magnetic core 6 of the present invention is made into two split molds so that it can be inserted into the parallel line 8, it can be attached to an existing line without cutting the line.
以上に述べたように本考案は既設の線路につい
ても安全に作業ができ、雑音除去最適位置を容易
に見つけ出し、平行線路の特性の向上をはかるこ
ともできる。 As described above, the present invention allows work to be carried out safely even on existing lines, easily finds the optimum position for noise removal, and improves the characteristics of parallel lines.
第１図は従来のウエーブトラツプの回路図で、
ａは並列共振回路、ｂは直列共振回路を平行線路
のの片側に挿入、ｃは並列共振回路を線路に、直
列共振回路を線路間に挿入した回路図、第２図は
本考案の平衡型ウエーブトラツプの実施例の実体
斜視図、第３図は本考案の平衡型ウエーブトラツ
プにおける等価回路図である。
図において、５：コンデンサ、６，６′：フエ
ライト磁心、７：導体、８，８：平行線路、９：
フエライト磁心の中心孔。
Figure 1 is a circuit diagram of a conventional wave trap.
a is a parallel resonant circuit, b is a series resonant circuit inserted on one side of the parallel lines, c is a circuit diagram with a parallel resonant circuit inserted in the line and a series resonant circuit inserted between the lines, and Figure 2 is the balanced type of the present invention. FIG. 3 is an actual perspective view of an embodiment of the wave trap, and is an equivalent circuit diagram of the balanced wave trap of the present invention. In the figure, 5: capacitor, 6, 6': ferrite core, 7: conductor, 8, 8: parallel line, 9:
Center hole of ferrite core.
Claims (1)
心孔内に貫通させた筒状フエライト磁心と、前記
両筒状フエライト磁心の中心孔に共通に巻回し、
この巻線をコンデンサの両端子に終端してなる平
衡型ウエーブトラツプ。 A cylindrical ferrite magnetic core in which each of the one or two parallel lines is passed through a center hole in the cylinder, and is commonly wound around the center hole of both the cylindrical ferrite magnetic cores,
A balanced wave trap consists of this winding being terminated at both terminals of a capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16700181U JPS5873623U (en) | 1981-11-11 | 1981-11-11 | Balanced wave trap |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16700181U JPS5873623U (en) | 1981-11-11 | 1981-11-11 | Balanced wave trap |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5873623U JPS5873623U (en) | 1983-05-18 |
| JPS6314520Y2 true JPS6314520Y2 (en) | 1988-04-22 |
Family
ID=29959126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16700181U Granted JPS5873623U (en) | 1981-11-11 | 1981-11-11 | Balanced wave trap |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5873623U (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2560491Y2 (en) * | 1987-01-30 | 1998-01-21 | 日本電気株式会社 | Longitudinal current blocking circuit of coaxial transmission line |
-
1981
- 1981-11-11 JP JP16700181U patent/JPS5873623U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5873623U (en) | 1983-05-18 |
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