JPS63142713A - Level shift circuit - Google Patents

Abstract

PURPOSE:To contribute a more flexible design and use by inserting a temperature compensation element which compensates the temperature characteristic of an MOS type electric field effect transistor in series with a load element to connect them. CONSTITUTION:A fourth MOS type FET 4 is used as the temperature compensation element and the gate electrode is connected to the source electrode of a third MOS type FET 3 as well as the drain electrode and then the source electrode is connected to a ground electric potential 10. Since the fourth MOS type FET 4 has the same connection as the first and the second MOS type FETs 1 and 2 the variation of a voltage between the source and the drain occurs in a same direction concerning the variation of the temperature. As a result as for the output voltage in an output terminal 8, the variation is reduced against a same input voltage.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a level shift I/circuit suitable for multi-value logic circuits, level detection circuits, etc., and in particular to semiconductor integrated circuit devices configured with MOS type field effect transistors. The present invention relates to a temperature-compensated level shifter 2I circuit formed in .

1. Prior Art] In recent years, semiconductor integrated circuit devices have become increasingly highly integrated, highly dense, and multifunctional, and have come to be applied to a wide variety of fields. With the integration of various functions, the number of input/output terminals of semiconductor integrated circuit devices continues to increase, and the packages of semiconductor integrated circuit devices inevitably become larger.
Problems with reduced mounting density on printed circuit boards, etc., or
Problems such as damage to silicon chips depending on package dimensions have also arisen.

Multivalued logic circuits have been proposed against this background, and for example, the number of input terminals can be halved by providing input with three logic levels. These three logic levels are, for example, 0 to 2.5V, 2.5 to 5V,
It is possible to set a potential of 5V or more, and a level shift circuit is used as a means for detecting this potential of 5V or more.

Conventionally, there is a level shift circuit shown in FIG. 4 that uses the high threshold logic level of this type of multivalued logic circuit in a detection circuit. In FIG. 4, a first MOS type field effect transistor (hereinafter referred to as MOS type FET) 1 has its gate electrode and drain electrode connected to an input terminal 7, and its source electrode is connected to the drain electrode of a third MOS type FET 3. and is connected to the output terminal 68. Third MOS type FET
3 is used as a load element, its gate electrode is biased to a power supply potential 9, and its source electrode is connected to a ground electrode 10.

Next, the operation of the conventional level shift circuit shown in FIG. 4 will be explained using the MOS type FET current-voltage characteristic diagram shown in FIG. The current-voltage characteristic of the first MOS type FET 1 when the first input voltage V is applied to the input terminal 7 is expressed as the fifth
FIG. 11 also shows that the first MO when a second input voltage V12 higher than the first input voltage V12 is applied to the input terminal 7.
The current-voltage characteristics of the S-type FET 1 are shown in FIG. 5, 12, and the current-voltage characteristics of the third MOS-type FET 3 are shown in FIG. 5, 13. The first and second input terminals 1 (, V
12 is applied, the output is at the intersection 14 of the current-voltage characteristic 11.13 and the current-voltage characteristic 1 in FIG. 5, respectively.
2.13 is indicated by the intersection 15.

The output voltage generated at the output terminal 8 of the circuit to level shift 1 in FIG. 4 is transferred to the third MOS type FET 3 as shown in FIG.
Considering that the fluctuation in the current-voltage characteristic 13 is minute, the voltage is lower than the input terminal by approximately the threshold voltage of the first MOS type FET. When the magnitude of this output voltage exceeds the input threshold of an inverting amplifier (not shown) connected to the output terminal of the level shift circuit, the inverting amplifier will invert its output.

Note that in order to reduce the input current of the level shift circuit, the third MOS type FET 3 usually has a channel length and channel width set such that mutual conductance is small. It is also possible to replace the third MOS type FET 3 with a resistive element, in which case a polycrystalline silicon resistor, a diffused resistor, an ion implanted resistor, etc. are used, as will be clear to those skilled in the art. Furthermore, it is possible to use a plurality of first MOS type FETIs connected in series, and in that case, it is clear that the amount of shift of the output voltage from the input voltage is adjusted depending on the number of the first MOS type FETIs connected in series. Probably.

[Problems to be Solved by the Invention, 1] As detailed above, in the conventional level shift circuit, the output voltage + input voltage) - (threshold voltage of the first MOS FETI) x (number of series) Therefore, the output voltage depends on the electrical characteristics of the threshold voltage of the first MOS type FET1 itself.

Normally, the operating range temperature of semiconductor integrated circuit devices is 0℃~
The temperature is about +85℃, and the amount of variation in the threshold I/hold voltage of the MOS type FET at this time is approximately -1.5 to -2.5m.
V/'C, the fluctuation in the output voltage of the level shift circuit is as follows for each unit connected in series to the same input terminal:
Approximately Oj V will be generated. Therefore, in the above-mentioned conventional level shift circuit, unless the input threshold of the inverter connected to its output is similarly varied, the input threshold varies with the ambient temperature and malfunctions. In addition, it has the disadvantage of being subject to various restrictions in use.

The purpose of the present invention is to eliminate the above-mentioned drawbacks with a simple configuration,
It is an object of the present invention to provide a level shift circuit that allows for more flexible design and use.

Means for Solving Problem 1] The level shift circuit of the present invention consists of one or more series-connected MOS FETs whose gate electrode is connected to a drain electrode and whose drain electrode and source electrode are input and output, respectively. The MO8 type PE has a two-terminal circuit connected between the logic signal input point and the output point, has a load element between the output point and the reference potential point, and is inserted and connected in series with the load element.
and a temperature compensation element that compensates for the temperature characteristics of T. Further, the present invention has a two-terminal circuit as a temperature compensating element by connecting one or more MOS FETs in series, the gate electrode of which is connected to the drain electrode, and the drain electrode and the source electrode used as input and output.

Furthermore, the present invention includes a forward biased PN junction diode as a temperature compensation element.

1 Example J Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of a level shift circuit of the present invention.

In FIG. 1, the gate electrode and drain electrode on the first MO8 type FEFET are connected to the input terminal 7, and the source electrode is connected to the drain electrode of the second MOS type FET2. The second MOS type FET 2 has its goo1 electrode connected to the drain electrode, and its source electrode connected to the output terminal 8 and the drain electrode of the third MOS type FE T3.

The third MOS type FET 3 is used as a load element, its gate electrode is biased to the power supply potential 9, and its source electrode is connected to the drain electrode of the fourth MOS type FET 4. The fourth MOS type FET 4 is used as a temperature compensation element, and its gate electrode is connected to the source electrode of the third MOS type FET 3 together with its drain electrode, and the source electrode is connected to the ground potential 10.

In the first embodiment, the fourth MOS type FET·l is the first MOS type FET·l. Since it has the same connection as the second MOS type FET I, 2, its source-drain voltage fluctuates in the same direction with respect to temperature fluctuations, and as a result, the output terminal 8
The amount of variation in the output voltage at is reduced for the same input terminal.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. In FIG. 2, 1. Second. Third. Fourth MOS type FE
TE, 2.3.4 are the same as the first embodiment, and the fifth
The gate electrode and drain electrode of the MO9O9 type FET 5 are connected to the fourth MO9O9 type FET 4 and the source electrode of the fifth MOS type FET 5 is connected to the ground potential 10. In the second example,
1st. The temperature variation of the shift l- amount generated by doubling the threshold voltage generated by the second MOS type FETI, 2 is calculated by the fourth. Since compensation is made based on temperature fluctuations in the threshold voltages of the fifth MO8 type FETs 4 and 5, the temperature compensation is even more excellent than that of the first embodiment. In addition, the fourth section used for temperature compensation. It is possible to further increase the number of fifth MO9O9 type FETs connected in series, but as the number increases, it is necessary to consider the increase in output voltage for the same input terminal, and there is a limit to the number of series connections. Needless to say.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention. Second. Third MO8 type FI TL
, 2.2 is the same as the first embodiment, and the PN junction diode 6 has its positive side electrode connected to the source electrode of the third MOS type 1''ET3 and its negative side electrode connected to the ground potential. .

PN junction diode is used in forward bias condition,
Its forward voltage, as is well known, has a temperature coefficient of about -2 mV/°C. Therefore, since this temperature variation is in the same direction as the temperature variation of the threshold voltage of the MOS type FE1, the level shift circuit is temperature compensated.

In addition, this PN junction diode is C-M OS 44'
In a conductor integrated circuit device, F' N between a - conductivity type well region and an opposite conductivity type source/drain diffusion layer region is
It is constructed by joining and joining, and does not require the addition of any new process. Also, the fourth section performs temperature compensation. Although the fifth MOS type FET 4.5 has been described with its gate electrode connected to the drain electrode, it is clear that the electrodes of the fifth MOS type FET 4.5 can be connected to a suitable power source.

In addition, in experiments conducted by the present inventor, the amount of variation due to temperature was approximately 509
It was reduced to 6.

[Effects of the Invention] As explained above, the present invention has the following advantages:
By introducing a temperature compensation element that changes the threshold voltage of the MO8 type FET, which determines the amount of shift, in the same direction as the temperature fluctuation, the degree of freedom in design and use can be expanded compared to conventional circuits. There is.

[Brief explanation of the drawing]

Figures 1 to 3 are the first to third level shift I/circuits of the present invention.
4 is a circuit diagram showing a conventional level shift circuit, and FIG. 5 is a current-voltage characteristic diagram of an MO8 type FET for explaining the operation of the level shift I circuit. 1... First MOS type FET, 2... Second MO8 type FET, 3... Third MOS type FET, 4... Fourth
MO8 type FET, 5...fifth MOS type FET
, f)..."N junction diode, 7... Input terminal, 8... Output terminal, 9... Power supply potential, 10... Ground potential, 11°12... First MO8 Current-voltage characteristics of type FET, 13...Current-voltage characteristics of third MOS type FET.

Claims (1)

[Claims] 1. A MOS in which the gate electrode is connected to the drain electrode, and the drain electrode and the source electrode are used as input and output, respectively.
A level shift circuit having a two-terminal circuit formed by one or more series-connected type field effect transistors between a logic signal input point and an output point, and having a load element between the output point and a reference potential point. , the M is connected in series with the load element.
A level shift circuit characterized in that a temperature compensation element is inserted and connected to compensate for the temperature characteristics of an OS type field effect transistor. 2. In the level shift circuit according to claim 1, the temperature compensating element is a MOS type field effect transistor whose gate electrode is connected to a drain electrode, and whose input and output are the drain electrode and the source electrode. A level shift circuit is a two-terminal circuit with one or more connected in series. 3. The level shift circuit according to claim 1, wherein the temperature compensation element utilizes forward characteristics of a PN junction diode.