JPS63142598A - Nonvolatile semiconductor storage device - Google Patents

Nonvolatile semiconductor storage device

Info

Publication number
JPS63142598A
JPS63142598A JP61288795A JP28879586A JPS63142598A JP S63142598 A JPS63142598 A JP S63142598A JP 61288795 A JP61288795 A JP 61288795A JP 28879586 A JP28879586 A JP 28879586A JP S63142598 A JPS63142598 A JP S63142598A
Authority
JP
Japan
Prior art keywords
voltage
circuit
power supply
verification
nonvolatile semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61288795A
Other languages
Japanese (ja)
Inventor
Koichi Seki
浩一 関
Takaaki Hagiwara
萩原 隆旦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP61288795A priority Critical patent/JPS63142598A/en
Publication of JPS63142598A publication Critical patent/JPS63142598A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To reduce the power supply by generating a voltage for verification in the inside of the storage device. CONSTITUTION:After the write, a switch 2 is thrown to a high voltage of a boosting circuit 1 and a voltage VH is fed to the final stage 3 of the row decoder circuit. In case of verification, a MOS transistor (TR) of diode connection of an extraction circuit 4 is conductive and the high voltage VH is decreased to a prescribed voltage. The voltage is applied to a word line through the final stage 3 of the row decoder to apply verification. Thus, no verification power supply is required and number of power supplies is decreased.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は不揮発性半導体記憶装置に係シ、特にオンボー
ド書込みに好適な内部回路を有する不揮発性半導体記憶
装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile semiconductor memory device, and particularly to a nonvolatile semiconductor memory device having an internal circuit suitable for on-board writing.

〔従来の技術〕[Conventional technology]

不揮発性半導体記憶装置のうち、紫外線消去型のもの、
 EPROM (Erasable Programm
ableRead Qnly Memory  )にお
いてはその書込方法として高速プログラムモードが一般
化してきている。(オーム社rLsI)\ンドブツク」
第2章p、519)このモードでは1バイト当シあらか
じめ決められた幅のパルスで書込みを行ない、その後読
取シを行ない、情報を確認(ベリファイ)する。これを
繰返して書込みがなされたと判断すると追加簀込みを行
ない1次のバイトに進む。通常のM、取りでは電源は5
■に設定するが、このベリファイにおいては6vとする
のが一般的である。
Among non-volatile semiconductor memory devices, those that can be erased by ultraviolet light,
EPROM (Erasable Program
A high-speed program mode is becoming common as a writing method for capableRead Qnly Memory). (Ohmsha rLsI)\Ndobook”
(Chapter 2 p. 519) In this mode, writing is performed with a pulse of a predetermined width per byte, and then reading is performed to verify the information. If this is repeated and it is determined that writing has been performed, additional storage is performed and the process proceeds to the first byte. Normal M, the power supply is 5
(2) However, in this verification, it is generally set to 6V.

これはこの17分のマージンを情報にもたせるためであ
る。
This is to provide information with a margin of 17 minutes.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記、従来技術では少なくとも2つの電源、書込み用の
v2.と呼ばれる高電圧電源も含めれば3つの電源を必
要としており、専用の書込み器を必要とする。
In the above-mentioned conventional technology, there are at least two power supplies, v2. It requires three power supplies, including a high-voltage power supply called ``, and a dedicated writer.

本発明の目的は必要とする電源の数をより少なくできる
不揮発性半導体記憶装置を得ることにある。
An object of the present invention is to obtain a nonvolatile semiconductor memory device that can reduce the number of required power supplies.

〔問題点’es決するための手段〕[Means to resolve the issue]

上記目的は記憶装置内部でベリファイ時に必要とする電
圧を発生させる事により達成される。
The above object is achieved by generating voltages required during verification within the memory device.

〔作用〕[Effect]

EFROM においては第2図に示すように1つのメモ
リ5を読出す際、それにつながるワード線6とビットI
w7を行デコーダ8と列デコーダ9により選択し、この
メモリを流れる電流の大小を情報に対応づけている。行
デコーダ8の最終段の電源V p cとしては読取シの
時はVcc(例えば5V)書込みの時には高電圧(例え
ば12.5V)となるような電源が接続されている。書
込み時には、メモリのゲートとドレインに高電圧を印加
するのが通常のEFROMを構成するFAMOS (F
loat ingQate Avalanche In
jection MOS  )メモリの簀込み方法であ
る。ベリファイ時にはVcc=6Vとし、この電源Vp
eにはV c cが加わるようになっている。よって高
電圧として外部電源によらず。
In EFROM, as shown in FIG. 2, when reading one memory 5, the word line 6 and bit I connected to it are
w7 is selected by the row decoder 8 and column decoder 9, and the magnitude of the current flowing through this memory is associated with information. As the power supply V p c of the final stage of the row decoder 8, a power supply is connected which is Vcc (for example, 5V) during reading and high voltage (for example, 12.5V) during writing. During writing, a high voltage is applied to the gate and drain of the memory in the FAMOS (F
loat ingQate Avalanche In
(MOS) is a memory storage method. At the time of verification, Vcc=6V, and this power supply Vp
Vcc is added to e. Therefore, it does not depend on an external power source as a high voltage.

周辺回路に加わるのと同じ電源Vccから昇圧された電
圧を用い、ベリファイ時にV p c ’t”高電圧側
に接続したまま、この電圧を6vまで引下げてやればワ
ード線6には6vが印加されてベリファイ動作を行なえ
る。
If you use a voltage boosted from the same power supply Vcc that is applied to the peripheral circuits and lower this voltage to 6V while connecting it to the high voltage side of V p c 't'' during verification, 6V will be applied to the word line 6. Verify operation can be performed.

〔実施例〕〔Example〕

以下1本発明を実施例により説明する。第1図はその構
成を示す。昇圧回路1.スィッチ21行デコーダ回路最
終段3.ベリファイ時に昇圧電圧を引下げる引抜き回路
4である。
The present invention will be explained below with reference to examples. FIG. 1 shows its configuration. Boost circuit 1. Switch 21 row decoder circuit final stage 3. This is a extraction circuit 4 that lowers the boosted voltage during verification.

図中v11とV12は互いに位相が逆相のパルスであシ
、このパルスで供給された電荷がダイオード接続されf
cMO8トランジスタを通して伝わっていき、最終段で
は高電圧として取出される。2は電圧安定化のためのツ
ェナーダイオードである。
In the figure, v11 and V12 are pulses whose phases are opposite to each other, and the charges supplied by these pulses are connected to a diode, f
It is transmitted through the cMO8 transistor and taken out as a high voltage at the final stage. 2 is a Zener diode for voltage stabilization.

Vwは書込み時にはHighとなる電圧信号である。Vw is a voltage signal that becomes High during writing.

昇圧回路1.スィッチ21行デコーダ回路最終段3.引
抜き回路4の具体例を第3図に示す。書込みを行なった
後ではスイッチ2は高電圧vH側に選択されて行デコー
ダ回路最終R3に供給されているのでベリファイ時には
切替えない。ベリファイ時には信号vlがHigh レ
ベルとなシ、この回路を通して昇圧回路から電流を流す
。一般的に昇圧回路1は一般の電源に比べて電流供給能
力が低いため、を圧が降下してくる(第4図)。引抜き
回路4のダイオード接続されたMOS)ランジスタによ
って設定された値に落ちつく。この電圧が行デコーダの
最終段を通してワード線、即ち読取るべきメモリのゲー
トに印加される。
Boost circuit 1. Switch 21 row decoder circuit final stage 3. A specific example of the extraction circuit 4 is shown in FIG. After writing, switch 2 is selected to the high voltage vH side and is supplied to the final row decoder circuit R3, so it is not switched during verification. During verification, when the signal vl is at a high level, current flows from the booster circuit through this circuit. Generally, the booster circuit 1 has a lower current supply capacity than a general power supply, so the voltage drops (FIG. 4). It settles on the value set by the diode-connected MOS) transistor of the extraction circuit 4. This voltage is applied through the last stage of the row decoder to the word line, ie to the gate of the memory to be read.

最近、読取pの高速化をめざしてA T D (Add
ressTransition 、[)etectio
nアドレス遷移検出)を用いたセンスアンプが使われる
ようになってきている。アドレス変化を検出してパルス
を発生させ。
Recently, ATD (Add
ressTransition , [) etectio
Sense amplifiers using n-address transition detection) have come into use. Detects address changes and generates pulses.

これを用いてあらかじめセンスアンプを平衡状態として
センスアンプの高速化をはかるものである。
Using this, the sense amplifier is brought into a balanced state in advance to increase the speed of the sense amplifier.

このようなセンスアンプの例を第5図に示す。上記パル
スから作シ出したパルスφによりMOSトランジスタ9
.10を通じてノードA、 Bをプリチャージしておき
、同時にMOSトランジスタ11でイコライズする。メ
モリ1とダミーメモリ14の能力差を利用して12.1
3のpチャネルMO8)ランジスタによりこれを増幅し
て情報を読取る。MOSトランジスタ15.16はメモ
リとダミーメモリのドレインの電位を適当な値に設定す
ると共に負荷側と分離する事によってアクセスの高速化
をはかるために用いている。
An example of such a sense amplifier is shown in FIG. The pulse φ generated from the above pulse causes the MOS transistor 9 to
.. Nodes A and B are precharged through MOS transistor 10 and equalized at the same time by MOS transistor 11. 12.1 using the difference in capacity between memory 1 and dummy memory 14
This is amplified by a p-channel MO8) transistor of 3 and the information is read. The MOS transistors 15 and 16 are used to set the drain potentials of the memory and dummy memory to appropriate values and to speed up access by separating them from the load side.

本発明はこのようなセンスアンプにも適用しうる。引抜
き回路4を第6図に示すように変更すると昇圧電位VH
が降下してきである判定レベルを越えると出力VR,が
反転する(第7図ン。この変化を検出して基準パルスを
第8図の構成のような回路で発生させ、さらにセンスア
ンプを駆動するのに適当なパルスに変形すれば良い。回
路17は遅延回路である。この回路を用いた場合IVH
は判定レベルを越えた後も降下を続けるが、その降下の
速度は遅く1判定から読取シに要する時間に比べて問題
とならないし、読取シ後センスアンプの出力をラッチ入
力してやればさらにその後の■Hの降下によっても出力
に影響は無い。
The present invention can also be applied to such a sense amplifier. When the extraction circuit 4 is changed as shown in FIG. 6, the boosted potential VH
When the voltage drops and exceeds a certain judgment level, the output VR is inverted (Fig. 7). This change is detected and a reference pulse is generated by a circuit as shown in Fig. 8, which further drives the sense amplifier. The circuit 17 is a delay circuit. When this circuit is used, IVH
continues to fall even after exceeding the judgment level, but the speed of the fall is slow and is not a problem compared to the time required from the first judgment to reading, and if the output of the sense amplifier is latched input after reading, the subsequent ■The drop in H does not affect the output.

本発明の適用範囲は上記具体的回路にとどまるものでは
なく、上述の概念を実現できるものであれば良い事は言
うまでもない。
Needless to say, the scope of application of the present invention is not limited to the above-mentioned specific circuit, but may be applied to any circuit that can realize the above-mentioned concept.

〔発明の効果〕〔Effect of the invention〕

本発明によれば書込み後のベリファイ時に外部Vccを
再設定する必要がない不揮発性半導体記憶装置を得るこ
とができる。
According to the present invention, it is possible to obtain a nonvolatile semiconductor memory device that does not require resetting external Vcc during verification after writing.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の概略構成を示す図、第2図は不揮発性
半導体記憶装置の構成を示す図、第3図は本発明の一実
施例を示す回路図、第4図は第3図を説明するだめのタ
イミングチャート図、第5乃至8図は本発明の他の実施
例を示す図。 1・・・昇圧回路、2・・・スイッチ、3・・・行デコ
ーダ回路最終段、4・・・引抜き回路、5・・・メモリ
、6・・・ワード線、7・・・ビット線、8・・・行デ
コーダ回路、9・・・列デコーダ回路。 l・・耳圧回蒔 2・・・スイッチ 3 ・付デジーダ回路景p陶愛 4・・・弓I丁友芳 回路 第 、5 図 第 6 凹
FIG. 1 is a diagram showing a schematic configuration of the present invention, FIG. 2 is a diagram showing a configuration of a nonvolatile semiconductor memory device, FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. FIGS. 5 to 8 are timing charts for explaining other embodiments of the present invention. DESCRIPTION OF SYMBOLS 1... Boost circuit, 2... Switch, 3... Row decoder circuit final stage, 4... Extraction circuit, 5... Memory, 6... Word line, 7... Bit line, 8... Row decoder circuit, 9... Column decoder circuit. L...Ear pressure turning 2...Switch 3, Digida circuit view p Sueai 4...Bow I Ding Tomoyoshi circuit No. 5, Fig. No. 6 concave

Claims (1)

【特許請求の範囲】 1、ソース、ドレイン又はゲートに電圧を印加する事に
よりしきい電圧を変えうる素子を記憶素子として有し、
該しきい電圧が所定の値又は所定の範囲に到達したか否
かを調べる手段を有し、該手段は電源電圧とは異なる電
圧を該記憶素子のゲート、ソース又はドレインに印加す
る手段を含み、該電源電圧とは異なる電圧は該集積回路
内部において設けられた電源回路から供給されている事
を特徴とする不揮発性半導体記憶装置。 2、該電源電圧とは異なる電圧は電源電圧より高い電圧
であり、これが該集積回路内部の昇圧回路により供給さ
れている事を特徴とする特許請求の範囲第1項記載の不
揮発性半導体記憶装置。
[Claims] 1. A memory element having an element whose threshold voltage can be changed by applying a voltage to the source, drain, or gate;
means for checking whether the threshold voltage has reached a predetermined value or a predetermined range, and the means includes means for applying a voltage different from the power supply voltage to the gate, source, or drain of the storage element. . A nonvolatile semiconductor memory device, wherein a voltage different from the power supply voltage is supplied from a power supply circuit provided inside the integrated circuit. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the voltage different from the power supply voltage is a voltage higher than the power supply voltage, and is supplied by a booster circuit inside the integrated circuit. .
JP61288795A 1986-12-05 1986-12-05 Nonvolatile semiconductor storage device Pending JPS63142598A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61288795A JPS63142598A (en) 1986-12-05 1986-12-05 Nonvolatile semiconductor storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61288795A JPS63142598A (en) 1986-12-05 1986-12-05 Nonvolatile semiconductor storage device

Publications (1)

Publication Number Publication Date
JPS63142598A true JPS63142598A (en) 1988-06-14

Family

ID=17734827

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61288795A Pending JPS63142598A (en) 1986-12-05 1986-12-05 Nonvolatile semiconductor storage device

Country Status (1)

Country Link
JP (1) JPS63142598A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05151789A (en) * 1991-11-29 1993-06-18 Nec Corp Electrically writable and batch erasable nonvolatile semiconductor memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05151789A (en) * 1991-11-29 1993-06-18 Nec Corp Electrically writable and batch erasable nonvolatile semiconductor memory device

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