JPS63142598A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the power supply by generating a voltage for verification in the inside of the storage device. CONSTITUTION:After the write, a switch 2 is thrown to a high voltage of a boosting circuit 1 and a voltage VH is fed to the final stage 3 of the row decoder circuit. In case of verification, a MOS transistor (TR) of diode connection of an extraction circuit 4 is conductive and the high voltage VH is decreased to a prescribed voltage. The voltage is applied to a word line through the final stage 3 of the row decoder to apply verification. Thus, no verification power supply is required and number of power supplies is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile semiconductor memory device, and particularly to a nonvolatile semiconductor memory device having an internal circuit suitable for on-board writing.

[Conventional technology]

Among non-volatile semiconductor memory devices, those that can be erased by ultraviolet light,
EPROM (Erasable Program
A high-speed program mode is becoming common as a writing method for capableRead Qnly Memory). (Ohmsha rLsI)\Ndobook”
(Chapter 2 p. 519) In this mode, writing is performed with a pulse of a predetermined width per byte, and then reading is performed to verify the information. If this is repeated and it is determined that writing has been performed, additional storage is performed and the process proceeds to the first byte. Normal M, the power supply is 5
(2) However, in this verification, it is generally set to 6V.

This is to provide information with a margin of 17 minutes.

[Problem that the invention seeks to solve]

In the above-mentioned conventional technology, there are at least two power supplies, v2. It requires three power supplies, including a high-voltage power supply called ``, and a dedicated writer.

An object of the present invention is to obtain a nonvolatile semiconductor memory device that can reduce the number of required power supplies.

[Means to resolve the issue]

The above object is achieved by generating voltages required during verification within the memory device.

[Effect]

In EFROM, as shown in FIG. 2, when reading one memory 5, the word line 6 and bit I connected to it are
w7 is selected by the row decoder 8 and column decoder 9, and the magnitude of the current flowing through this memory is associated with information. As the power supply V p c of the final stage of the row decoder 8, a power supply is connected which is Vcc (for example, 5V) during reading and high voltage (for example, 12.5V) during writing. During writing, a high voltage is applied to the gate and drain of the memory in the FAMOS (F
loat ingQate Avalanche In
(MOS) is a memory storage method. At the time of verification, Vcc=6V, and this power supply Vp
Vcc is added to e. Therefore, it does not depend on an external power source as a high voltage.

If you use a voltage boosted from the same power supply Vcc that is applied to the peripheral circuits and lower this voltage to 6V while connecting it to the high voltage side of V p c 't'' during verification, 6V will be applied to the word line 6. Verify operation can be performed.

〔Example〕

The present invention will be explained below with reference to examples. FIG. 1 shows its configuration. Boost circuit 1. Switch 21 row decoder circuit final stage 3. This is a extraction circuit 4 that lowers the boosted voltage during verification.

In the figure, v11 and V12 are pulses whose phases are opposite to each other, and the charges supplied by these pulses are connected to a diode, f
It is transmitted through the cMO8 transistor and taken out as a high voltage at the final stage. 2 is a Zener diode for voltage stabilization.

Vw is a voltage signal that becomes High during writing.

Boost circuit 1. Switch 21 row decoder circuit final stage 3. A specific example of the extraction circuit 4 is shown in FIG. After writing, switch 2 is selected to the high voltage vH side and is supplied to the final row decoder circuit R3, so it is not switched during verification. During verification, when the signal vl is at a high level, current flows from the booster circuit through this circuit. Generally, the booster circuit 1 has a lower current supply capacity than a general power supply, so the voltage drops (FIG. 4). It settles on the value set by the diode-connected MOS) transistor of the extraction circuit 4. This voltage is applied through the last stage of the row decoder to the word line, ie to the gate of the memory to be read.

Recently, ATD (Add
ressTransition , [) etectio
Sense amplifiers using n-address transition detection) have come into use. Detects address changes and generates pulses.

Using this, the sense amplifier is brought into a balanced state in advance to increase the speed of the sense amplifier.

An example of such a sense amplifier is shown in FIG. The pulse φ generated from the above pulse causes the MOS transistor 9 to
．． Nodes A and B are precharged through MOS transistor 10 and equalized at the same time by MOS transistor 11. 12.1 using the difference in capacity between memory 1 and dummy memory 14
This is amplified by a p-channel MO8) transistor of 3 and the information is read. The MOS transistors 15 and 16 are used to set the drain potentials of the memory and dummy memory to appropriate values and to speed up access by separating them from the load side.

The present invention can also be applied to such a sense amplifier. When the extraction circuit 4 is changed as shown in FIG. 6, the boosted potential VH
When the voltage drops and exceeds a certain judgment level, the output VR is inverted (Fig. 7). This change is detected and a reference pulse is generated by a circuit as shown in Fig. 8, which further drives the sense amplifier. The circuit 17 is a delay circuit. When this circuit is used, IVH
continues to fall even after exceeding the judgment level, but the speed of the fall is slow and is not a problem compared to the time required from the first judgment to reading, and if the output of the sense amplifier is latched input after reading, the subsequent ■The drop in H does not affect the output.

Needless to say, the scope of application of the present invention is not limited to the above-mentioned specific circuit, but may be applied to any circuit that can realize the above-mentioned concept.

〔Effect of the invention〕

According to the present invention, it is possible to obtain a nonvolatile semiconductor memory device that does not require resetting external Vcc during verification after writing.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a schematic configuration of the present invention, FIG. 2 is a diagram showing a configuration of a nonvolatile semiconductor memory device, FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIG. FIGS. 5 to 8 are timing charts for explaining other embodiments of the present invention. DESCRIPTION OF SYMBOLS 1... Boost circuit, 2... Switch, 3... Row decoder circuit final stage, 4... Extraction circuit, 5... Memory, 6... Word line, 7... Bit line, 8... Row decoder circuit, 9... Column decoder circuit. L...Ear pressure turning 2...Switch 3, Digida circuit view p Sueai 4...Bow I Ding Tomoyoshi circuit No. 5, Fig. No. 6 concave

Claims (1)

[Claims] 1. A memory element having an element whose threshold voltage can be changed by applying a voltage to the source, drain, or gate;
means for checking whether the threshold voltage has reached a predetermined value or a predetermined range, and the means includes means for applying a voltage different from the power supply voltage to the gate, source, or drain of the storage element. . A nonvolatile semiconductor memory device, wherein a voltage different from the power supply voltage is supplied from a power supply circuit provided inside the integrated circuit. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the voltage different from the power supply voltage is a voltage higher than the power supply voltage, and is supplied by a booster circuit inside the integrated circuit. .