JPS63142452A - Interruption queue control system for system reset interruption - Google Patents

Abstract

PURPOSE:To eliminate a need of system reset processing by setting a system reset interruption to the queue pointed with a first interruption queue address pointer when previously queued interruption requests are all cleared. CONSTITUTION:A queue mechanism 31 is provided with a first interruption queue address pointer 31a and an address pointer to be next queued. If the system reset interruption request to clear all of previous interruption requests already queued in the queue mechanism 31 occurs, this interruption request is set to the queue pointed by the first interruption queue address pointer 31a, and the queue following this queue is pointed by the address pointer 31b to be next queued, and interruption requests are processed from the interruption request set to the queue pointed by the first interruption queue address pointer 31a.

Description

[Detailed Description of the Invention] [Summary] For example, in an interrupt control method such as a service processor (SVP) that queues and processes interrupt requests from a channel device, system reset interrupts such as temporary input/output interface errors, etc. When clearing all previously queued interrupt requests such as
By setting the system reset interrupt, it is possible to process a plurality of consecutive system resets as one time without clearing the previous interrupt queue.

[Industrial application field]

The present invention provides interrupt control when a system reset interrupt such as a temporary input/output interface error occurs in an interrupt control method that queues and processes interrupt requests from a channel device, such as a service processor (SVP). Regarding the method.

In the computer system, a service processor (SVP) is connected to -a, and manages maintenance, operation, etc.

In this case, from an economic perspective, the service processor (SV)
The processing speed of P) is usually only an acceptable processing speed, even if it is slower to some extent than the main device.

In other words, during normal maintenance, the service processor (S
The service processor (SVP) mainly controls the main unit via the system control interface (SCI), so the processing speed is sufficient to allow maintenance. When used as a console, high-speed processing is required to improve the man-machine interface.

Therefore, interrupt requests generated from the main unit at high speed for the console operation are processed first in the service processor (SVP) by the channel interface.
queuing to a queuing mechanism controlled by IFO),
It has a sequential processing mechanism.

Therefore, the channel device and service processor (SVP)
In the case of system reset or select preset processing that is required when an error occurs in the input/output interface between the two, it is necessary to clear the multiple interrupt requests queued in the queue mechanism before performing the above reset processing. There is a problem that the above-mentioned high-speed processing cannot be fully utilized.

In view of these circumstances, in an interrupt control method that processes multiple interrupts by queuing them, we developed an interrupt control method that effectively performs a reset interrupt that requires clearing the interrupt requests that have already been queued. A method is needed.

[Prior art and problems to be solved by the invention] Figure 2 is a diagram illustrating a conventional interrupt control method. In the computer system shown in Figure (a), there is a service that manages the maintenance and operation of the computer system. If a processor (SVP) 3 is connected and the service processor (SVP) 3 is used as a console during system operation,
It appears as one device connected to the channel device (CIIP) 2, and the central processing unit (CPU) 1 issues an input/output instruction (510) and the channel device (CIIP)
) 2 receives the input/output command (SIO), it retrieves the channel command word (CCW) set on the main memory (MS) 4, and sends it to the service via the multiplex channel adapter (MXCA) 3a. Performs input/output interrupts to processor (SVP) 3.

Koto multiplex channel adapter (MXC^) 3
The service processor (SVP) 3 queues the above-mentioned input/output interrupt request coming from a to the queue mechanism 31, performs input/output processing in a first-in, first-out (FIFO) format, and sends the input/output request to the device adapter (Ko A), for example. 3b, the data is output and displayed on the display 5a.

When sending data from the console 5 of the service processor (SVP) 3, the console 5 sends data to the service processor (SVP) 3. Channel apparatus (C liver)
Generates an attention interrupt to the central processing unit (CPU) 1 through the service processor (SVP) 2.
3 displays the above-mentioned sending data on the display 5a, and transmits the data to the service processor (SVP).
The channel device (CIIP) 2 receives the data from 3 and transfers it to the main storage device (MS) 4.

A service processor (SVP) handles such interrupts.
When processing within 3, channel device (CIIP) 2
They are sequentially input into the queue pointed to by the "next queue address pointer" 31b of the queue mechanism 31 (first-in, first-out FIFO) format, and the "first interrupt queue address pointer" 31a points to the queue mechanism 31. Queue interrupt information (processed sequentially starting from 11).

Here, if a failure occurs in the input/output interface between the channel device (CIIP) 2 and the service processor (SVP) 3 and, for example, the aforementioned selective reset interrupt occurs, the previous interrupt information ( 1), (2)
In order to disable the interrupt, clear the interrupt information (1) and (2), and then queue the select preset interrupt in the queue pointed to by the "address pointer to be queued next" 31b. The "first interrupt queue address pointer" 31a points to the select preset interrupt information, and processing begins with the select preset interrupt. Such system reset interrupts are generated by the central processing unit (CPU).
It also arises from 1.

Therefore, in conventional queuing processing, when a reset interrupt occurs such as the system reset or selectivity preset mentioned above, the previously queued interrupt information (1), (2), etc. After clearing, it is necessary to queue the system reset or select preset interrupt at the next position of the final queue, which causes a problem in that the response to console operations becomes slow.

SUMMARY OF THE INVENTION In view of the above-mentioned drawbacks of the conventional technology, it is an object of the present invention to provide a system for controlling system reset interrupts without clearing previously queued interrupt information.

[Means for solving problems]

FIG. 1 is a diagram showing an example of the configuration of an interrupt queue control method for system reset/7 interrupts according to the present invention.

In the present invention, there is provided an interrupt control mechanism that queues and processes a plurality of interrupt requests that occur sequentially in a queuing mechanism 31 that includes a first interrupt queue address pointer 31a and an address pointer 31b that should be first queued. When a system reset interrupt request to clear all previous interrupt requests already queued in the queue mechanism 31 occurs, the first interrupt queue address pointer 31a points to the interrupt request. The address pointer 31b points to the queue next to the queue in which the interrupt request is set, and the address pointer 31b points to the queue next to the queue in which the interrupt request is set, and the interrupt request is set in the queue pointed to by the first interrupt queue address pointer 31a. Configure to process.

[Effect]

That is, according to the present invention, for example, a service processor (
Clears all previously queued interrupt requests, such as system reset interrupts such as temporary input/output interface errors, in interrupt control methods that queue and process interrupt requests from channel devices, such as SVP). By setting the system reset interrupt in the queue pointed to by the first interrupt queue address pointer, you can avoid clearing the previous interrupt queue (and make multiple consecutive system resets appear as one). Therefore, even if a system reset interrupt occurs, the previously queued interrupt information is not cleared, and the next address pointer to be queued is simply changed. This has the effect that the application side does not have to perform system reset processing for the number of consecutive occurrences.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

The above-mentioned FIG. 1 is a diagram showing a configuration example of the interrupt queue control method for system reset interrupt of the present invention.
The present invention is implemented by means of setting (overwriting) a system reset interrupt for the queue 31 pointed to by the "first interrupt queue address pointer" 31a and changing the point address of the "address pointer to be queued next" 31b. It is a necessary means. In addition, throughout the diagram,
The same reference numerals indicate the same objects.

Hereinafter, an interrupt control method for a system reset interrupt according to the present invention will be explained with reference to FIG.

Even if the present invention is implemented, the normal interrupt processing from the channel device (CHP) 2 to the service processor (SVP) 3 will not change in particular, so it will be omitted here. The reset interrupt queue control method of the present invention will be described with a focus on the system reset interrupt operation in response to a failure occurring in the input/output interface between the service processor (SVP) 3 and the like.

First, as shown in FIG. 1(a), interrupt information (1
) and (2) are queued in the interrupt queue mechanism 31, and the "first interrupt queue address pointer" 31a
points to the first queue of the queue mechanism 31, and [address pointer to be queued next] 31b
Assume that the system reset interrupt described above occurs when the interrupt queue is pointing to the next interrupt queue.

At this time, the previously queued interrupt information (1) and (2) must be invalidated, but in the present invention, as shown in FIG. The system reset interrupt is overwritten in the queue at the position pointed to by the "include queue address pointer" 31a, and the "address pointer to be queued next" 31
Change the point destination of b to the next queue position of the queue where the system reset interrupt is set.

As a result, the above "first interrupt queue address pointer" 3
Interrupt information indicated by 1a (i.e. system reset interrupt)
The interrupt request that occurs next to the system reset interrupt is processed from the queue 31 to which the "address pointer to be queued next" 31b points.
Therefore, there is no need to clear the previously queued interrupt information (1) and (2) as in the conventional case.

When such system reset interrupts occur consecutively, the separate interrupts are always queued in the queue at the head position, so that the multiple system resets are processed only once for the application side. Since only the error can be seen, there is no need to perform system reset processing for the number of consecutive occurrences.

As described above, the present invention queues and processes multiple interrupt requests that occur sequentially in a queuing mechanism that includes a "first interrupt queue address pointer" and "an address pointer to be queued next." In a device equipped with an interrupt control mechanism, when an interrupt such as a system reset occurs that requires invalidating previously queued interrupt information, the system reset interrupt is overwritten in the first queue. The feature is that the "address pointer to be queued next" points to the next queue.

〔Effect of the invention〕

As described above in detail, the interrupt queue control method for system reset interrupts of the present invention is applicable to an interrupt control method that queues and processes interrupt requests from a channel device, such as a service processor (SVP), for example. When clearing all previously queued interrupt requests, such as a system reset interrupt such as a temporary input/output interface error, etc., set the system reset interrupt in the queue pointed to by the first interrupt queue address pointer. As a result, the previous interrupt queue is not cleared, and multiple consecutive system resets are treated as one, so even if a system reset interrupt occurs, the interrupt queue that was previously queued is not cleared. It is possible to simply change the destination of the next address pointer to be queued without clearing the current interrupt information, and the application side does not have to perform system reset processing for the number of consecutive interrupts. There is an effect.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a configuration example of an interrupt queue control method in system reset 7) interrupt of the present invention. FIG. 2 is a diagram explaining a conventional interrupt queue control method. It is. In the drawings, 1 is a central processing unit (CPU), 2 is a channel device (
CHP). 3 is a service processor (SVP). 4 is the main memory (MS), 5 is the console. 31 is a queue mechanism or queue. 31a is a first interrupt queue address pointer. 31b is an address pointer to be queued next. are shown respectively.

Claims (1)

[Claims] A plurality of interrupt requests that occur sequentially are queued in a queue mechanism (31) that includes a first interrupt queue address pointer (31a) and an address pointer (31b) to be queued next. In a device equipped with an interrupt control mechanism that processes interrupts, when a system reset interrupt request that clears all previous interrupt requests already queued in the queue mechanism (31) occurs, the interrupt request is The interrupt queue address pointer (31a) is set in the queue pointed to, and the address pointer (31b) to be queued next points to the queue next to the queue where the interrupt request is set, and the address pointer (31b) points to the queue next to the queue where the interrupt request is set, and An interrupt queue control method for system reset interrupts, characterized in that interrupt requests set in a queue indicated by an address pointer (31a) are processed first.