JPS6314215A - Reduction system for current consumption - Google Patents

Abstract

PURPOSE:To maintain system timing almost at the time of switching and reduce the current consumption of a circuit by supplying a clock signal of frequency corresponding to an execution speed in synchronism with the leading or trailing edge of a clock signal before the switching. CONSTITUTION:A programmable frequency dividing circuit 4 opens and closes a gate with a switching signal 5 from a synchronous binary counter and an MPU 7 and consists of a decoding circuit which decodes the output of the counter and an FF circuit which converts the decoding output into pulses with a 50% duty factor. Then, 2<1>-2<4> are counted firstly with signals (a-d) 5, and 1/2 frequency division is carried out by the FF circuit, so the frequency of a basic clock 3 can be varied up to 1/4-1/32 in synchronism with its clock. Further, frequency switching is postphoned until the trailing edge of the clock 3 appears after the application of the signals 5, so the switching is performed smoothly. Further, an IC group 8 decreases in current consumption proportionally according to a decrease in operating frequency, so the current consumption is reduced when the frequency is lowered.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to reducing the current consumption of electronic equipment, and in particular to CMO.
The present invention relates to a current consumption reduction method suitable for battery driving of electronic equipment configured with S-type active elements.

[Conventional technology]

In electronic equipment, the method of switching the clock signal frequency according to the required processing speed and reducing current consumption is as follows.
As seen in Japanese Unexamined Patent Publication No. 59-62933, the frequency dividing circuit has been realized by a circuit including a multiplexer and the like. However, when switching the frequency of the clock signal, no consideration was given to synchronizing and maintaining the timing of the entire system.

[Problem that the invention seeks to solve]

In the above conventional technology, when switching the frequency of the clock signal, a multiplexer selects one of the multiple clocks after the clock signal is divided, and no consideration is given to the periodization of the clock signal before and after switching. It wasn't. That is, there is a problem in that the clock signal becomes discontinuous when the clock signal is switched, and the operation timing of the entire system is adversely affected. Furthermore, when performing synchronization, it is necessary to add a corresponding circuit (synchronization circuit), complicating the system.

An object of the present invention is to provide a method of reducing current consumption while maintaining the operating timing of the entire system by synchronizing the frequency switching of a clock signal before and after the switching without requiring any particular synchronization circuit. It's about presenting.

[Means for solving problems]

The above purpose is to provide a clock signal with a frequency that matches the execution speed required for each processing of the device, by providing a clock signal that is synchronized with the rising or falling edge of the clock signal that was being supplied before switching. achieved.

As an example of a concrete measure, the multiplexer conventionally attached to the output of the frequency divider circuit may be removed and a programmable frequency divider circuit may be used.

[Effect]

The system clock supply circuit supplies a system clock of a frequency corresponding to the required execution speed of the device, either by hardware or software.

However, the clock frequency switching is performed in synchronization with the rising or falling edge of the clock before switching.

Since the current consumption of the C-MO5 circuit is proportional to the operating frequency, as the clock frequency decreases, the current consumption of the device decreases proportionally. Furthermore, since the clock is switched in synchronization with the clock before switching, the timing of the entire system is guaranteed.

〔Example〕

An embodiment of the present invention will be described below. FIG. 1 shows a block diagram of one embodiment.

In the first embodiment, a basic clock generation circuit 2 has an internal basic clock generating circuit 2. A clock 6 having a frequency division ratio specified by a basic clock 3 is sent to an MPU 7 by a command 5 from a microprocessor (hereinafter referred to as MPU).
Programmable frequency divider circuit 4, T around MPU
It consists of a TL and C-MO5 IC group 8, and processing circuits A-C (9 to 11) controlled by an MPU. Note that the processing circuits A to C have operating frequencies of f^ to fc, respectively.

FIG. 2 shows the basic clock 3 of the first embodiment and the divided clocks 61 to 63 (frequency f^ and fB, respectively).

fc) Waveforms of the MPU applied clock 64 during asynchronous switching and the MPU applied clock 6 during synchronous switching are shown. When the frequency is switched using the conventional asynchronous method, the frequency is switched at the same time as the switching signal 5 is applied, so the clock expands and contracts before and after switching, making it impossible to maintain the timing of the entire system. (Clock 64)-6 According to this embodiment, after the switching signal 5 is applied, frequency switching is postponed until the falling edge 30 of the basic clock appears, so that smooth frequency switching is possible. (Clock 6) Figure 3 shows the operating frequency vs. current consumption characteristics of the IC.
This is shown for O5IC10 and TTLIC20. Since the C-MO5 IC 10 has a characteristic that the current consumption decreases proportionally as the operating frequency decreases, when the frequency is lowered by the synchronous switching method, the current consumption in the C-MO3 circuit can be reduced.

FIG. 4 shows a concrete example of a single gravity type.

The programmable frequency dividing circuit 4 includes a synchronous pinary counter 46 (Q^ to Qo are count outputs) and a decoding circuit (41 to 45) that opens and closes the gate and decodes the counter in response to a switching signal a=d from the MPU 7. It consists of a flip-flop circuit that converts the output into a pulse with a duty of 50%. In the case of this embodiment, a count of 21 to 24 is first made by the switching signal a"d, and the frequency is further divided into 1/2 by the flip-flop circuit, so the overall frequency division ratio is 1/4 to 24. In other words, the frequency of the basic clock 3 can be changed from 1/4 to 1/32 (the denominator is an integer) in synchronization with that clock.

FIG. 5 shows another embodiment of this system.

The programmable frequency divider circuit 4 consists of a synchronous preset type frequency divider 40 (D^ to DD are preset inputs) and a flip-flop circuit that converts the frequency division 8 power into a pulse with a duty of 50%, and is implemented in the implementation area shown in Fig. 4. Compared to this, a decoding gate is not required.

In the case of this embodiment as well, 1/2 is determined by the switching signal a ” d.
Since the frequency is divided from 1 to 1/2 and further divided by 1/2 by a flip-flop, the frequency of basic clock 3 is synchronized with that clock and is 1/4 to 1/32 (however, the denominator is can be changed up to an integer).

FIG. 6 is an example of a program flowchart when implementing this method, and when operating six processing circuits A to C,
At the beginning of the program, an operating frequency is set according to the processing circuit, and processing is executed.

During standby, the clock frequency is set to the lowest (here, f^) in preparation for the next process.

This makes it possible to minimize current consumption during processing standby.

〔Effect of the invention〕

According to the present invention, when switching the frequency of the clock applied to the MPU, it is possible to switch the frequency in synchronization with the basic clock, so that the system clock before and after switching can be switched smoothly, while maintaining the timing of the entire system. The current consumption can be reduced. Furthermore, since no special circuit is required for synchronization, the circuit can be simplified.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a diagram of clock waveforms applied to the MPU according to the present invention and the conventional method. FIG. 3 is an operating frequency-current consumption characteristic diagram of C-MO5IC and TTLIC. FIGS. 4 and 5 are diagrams of a specific embodiment of the present invention. The system diagram, FIG. 6, is a program flowchart when using one embodiment of the present invention. 2... Basic clock generation circuit, 4... Programmable frequency dividing circuit, 6... Clock applied to MPU, 7...
・MPU, 40...Synchronous programmable divider,
Line 1 Figure 5 --- Ml'U ff 1 side 1C stone sanding 2 Figure 11 Shit ffi lower local skin t Shi;n 2 Io --- c-M? ) S IC 2O---TTL IC High 6th figure

Claims (1)

[Claims] 1. In electronic equipment that includes C-MOS type active elements and a clock generation circuit that controls their operation timing, and is capable of switching the clock frequency, a function that allows the clock frequency to be switched in synchronization with the rising or falling edge of the basic clock. A current consumption reduction method characterized by the provision of a frequency switching circuit.