JPS63141130A - Instruction prefetching device - Google Patents

Abstract

PURPOSE:To accelerate a CPU processing operation and to prevent the unauthorized access of a program from being performed by using a specific pattern, by enabling the pattern of an instruction to be prefetched to be set freely in an instruction analysis memory part. CONSTITUTION:An address signal outputted for the read of the next execution instruction from a CPU is latched by an address analysis memory part 2 in an instruction prefetching device 15, then is analyzed, and it is checked whether the said instruction already exists in a prefetch instruction buffer 5. When the instruction exists by prefetching, the instruction in the buffer 5 is immediately sent to the CPU1. Meanwhile, when no instruction exists, the instruction read out from an instruction memory device to the CPU1 by the address signal is latched by the instruction analysis memory part 3 in the instruction prefetching device 15, and it is checked whether the instruction is a specific instruction having a specific pattern or not.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a method for fetching and storing an instruction to be executed next by a central processing unit (CPU) from an instruction storage device.
The present invention relates to an instruction prefetching device that supplies instructions to a CPU when necessary, and relates to an instruction prefetching device that can be applied to general computer application products incorporating a CPU.

[Conventional technology]

Conventional instruction prefetching devices are based on a microprogram method, such as the one proposed in Japanese Patent Application Laid-open No. 181930/1983 (in the execution of a conditional branch type instruction, read access of the next instruction when the condition is not met, and This speeds up the instruction execution time by performing read access of the branch instruction in parallel when the branch instruction is established, enabling high-speed control)
For example, a method of pre-empting under special conditions as proposed in Japanese Patent Application Laid-Open No. 60-181931 (
When executing a conditional branch instruction, by predicting whether the condition is satisfied or not based on past information, the instruction that follows the conditional branch instruction is preempted, reducing wasted time accessing the main memory) The former is based on microprogram control and cannot be applied to existing CPUs, and the latter is only applicable to special CPUs. be.

[Problem that the invention seeks to solve]

In the conventional instruction prefetching device as described above, the address of the instruction to be prefetched is fixed.

For example, prefetching after executing a conditional branch type instruction is fixed in that it can only prefetch either the next instruction when the condition is not met or the next instruction when the condition is met. If a prefetch mechanism is included that considers both when the condition is met and when the condition is not met, the efficiency of executing conditional branch type instructions will be considerably improved.

However, in cases other than conditional branch instructions, for example DIV
When an instruction (such as a division instruction) that takes a long time to execute inside the CPU is being executed, it is not possible to prefetch multiple instructions.

The problem to be solved by the present invention is to make the address of an instruction to be prefetched not fixed but freely settable, and to make instruction prefetching applicable to existing CPUs.

[Means for solving problems]

The instruction prefetching device according to the present invention comprises a central processing unit (CP).
U) is configured as an instruction prefetching device that prefetches the next instruction to be executed from the instruction storage device, stores it, and supplies it to the CPU when it is needed.
and a bus for the CPU to access an instruction storage device, thereby providing the CPU with an instruction prefetching function.

The instruction prefetching device according to the present invention includes an address analysis storage section for separately capturing, storing, and analyzing an address signal outputted by the CPU in order to read an instruction from the instruction storage device, and an address analysis storage section for separately capturing, storing, and analyzing an address signal that the CPU outputs in order to read an instruction from the instruction storage device; An instruction analysis storage section for separately fetching, storing and analyzing instructions read out from the device, and when it is determined that the instruction read out is a certain specific instruction as a result of analysis in the instruction analysis storage section. , the instruction that has been read out from the instruction analysis storage section is sent and inputted, and the address signal corresponding to the instruction that has been read out is also inputted from the address analysis storage section, and an instruction that should be preempted from both of them. an address calculation unit that calculates the address of the address by calculation; a prefetch instruction buffer that stores an instruction that has been prefetched according to the address calculated by the calculation;
When the CPU outputs an address signal for reading the next instruction to be executed, the address analysis storage unit takes in the address signal, and as a result of analysis, it is determined that the instruction has already been prefetched and stored in the buffer. and a circuit for reading the information from the buffer and supplying it to the CPU when the information is determined.

[Effect]

The address signal output from the CPU for reading the next execution instruction is latched into the address analysis storage section in the instruction prefetching device and analyzed to determine whether the execution instruction has already been prefetched and exists in the prefetching instruction buffer. It is checked whether or not. If the instruction exists, the instruction in the buffer is immediately sent to the CPU.

If not, the instruction read from the instruction store to the CPtJ by that address signal is latched into the instruction parsing store in the instruction prefetcher and parsed to determine if it is a specific instruction with a specific pattern. , is checked. If it is a specific instruction, the instruction is sent to the address calculation section, and the address signal corresponding to the instruction latched in the address analysis storage section is also sent to the address calculation section.

The address calculation unit calculates the address of the instruction to be prefetched from both of them, prefetches the instruction according to the address and stores it in the prefetch instruction buffer during a period when the CPU is not performing reading/writing (READ/WRITE). .

The instruction prefetching operation is executed by repeating the above operations.

〔Example〕

The present invention will now be described in detail with reference to the drawings.

The figure is a block diagram showing one embodiment of the present invention.

In the figure, 1 is a CPU (a central processing unit that has the function of preempting the next instruction when a conditional branch is established), 2
is an address analysis storage unit, 3 is an instruction analysis storage unit, 4 is an address calculation unit, 5 is a prefetch instruction buffer, and 6 is an R/W (
read/write) direction control unit, 11.11A are data buses, 12.12/A are address buses, and 13.13A are R/W111? ill line,
15 is an instruction prefetching device according to the present invention.

As already mentioned, the CPUI is a central processing unit that has the function of preempting the next instruction when a conditional branch is established. C
The PUI is connected to the data bus 11. When a conditional branch type instruction is read from an instruction storage device (not shown) connected to the address bus 12, the instruction is analyzed by the instruction analysis storage section 3 in the instruction prefetching device 15 and recognized as a specific instruction. Ru. Then, the instruction is passed to the address calculation section 4. In addition, in order to read the conditional branch type instruction, the CPU
Since the address previously sent to the address bus 12 is stored in the address analysis storage section 2, this address is also passed to the address calculation section 4. The address calculation unit 4 calculates the address of the instruction when the conditional branch is not taken from the address and the instruction, waits for the end of the instruction prefetch period of the CPU 1, and sends the address onto the address bus 12. The instruction at the address is read into the prefetch instruction buffer 5 via the data bus 11. Also, the address passed to the address calculation unit is returned to the address analysis storage unit 2.
Return it to

When the conditional branch type instruction fails, cpUl outputs the address of the next instruction from address bus 12A.

The address is analyzed in the address analysis storage section 2, that is, it is compared with the previous address, and it is recognized that it has already been read into the prefetch instruction buffer 5. After recognition, the instruction is taken out from the buffer 5 and output to the CPUI via the instruction analysis storage section 3 and data bus IIA.

At that time, the read completion (READ completion) signal is R/W
It is output from the direction control section 6.

As described above, according to this embodiment, it is possible to preempt even when a conditional branch is not taken, and the parallel processing time for accessing the instruction storage device and the CPU internal processing is expanded, thereby further improving the CPU processing operation. Speed-up can be achieved.

Although the above description has been made using a conditional branch type instruction as an example, the instruction is not limited to this, and may be, for example, the above-mentioned DIV instruction (division instruction). When the DI instruction is recognized in the instruction analysis storage unit 3, it takes time to execute it on the CPUI, so the address calculation unit 4 reads the DrV instruction from the instruction analysis storage unit 3 and from the address analysis storage unit 2. Given the address signal, the addresses of multiple instructions following the DIV instruction can be calculated and sent to the instruction storage device, and the multiple instructions can be prefetched and stored in the prefetch instruction buffer 5. can.

〔Effect of the invention〕

According to the present invention, by freely setting the pattern of instructions to be prefetched in the instruction analysis storage section, not only can CPU processing operation be made faster, but also when a special pattern is input to the instruction analysis storage section. , CP special code
By inputting data to U, important parts of the program can be hidden from being read by others.

In addition, the instruction protection function can be realized using only the functions of the address analysis section and the instruction sending section without using the instruction analysis section.

[Brief explanation of the drawing]

The figure is a block diagram showing one embodiment of the present invention. Explanation of symbols 1...Central processing unit having a function of pre-fetching the next instruction when a conditional branch is established, 2...Analysis storage unit for READ addresses from the CPU, 3...Analysis of instructions read into the CPU Storage unit, 4... A calculation unit for the address of the instruction to be prefetched, 5... Prefetching instruction buffer, 6... R/W
direction control section

Claims (1)

[Claims] 1. The instruction to be executed next by the central processing unit (CPU) is
In an instruction prefetching device that prefetches an instruction from an instruction storage device, stores it, and supplies it to the CPU when necessary, the address signal output by the CPU to read an instruction from the instruction storage device is separately captured and stored. an address analysis storage section for analysis, an instruction analysis storage section for separately capturing, storing and analyzing the instructions read out from the instruction storage device by the CPU in accordance with the address signal, and the results of the analysis in the instruction analysis storage section; When the read instruction is found to be a certain specific instruction, the read instruction is sent from the instruction analysis storage section and input, and at the same time, the read instruction is also read from the address analysis storage section. an address calculation section which receives an address signal corresponding to an instruction and calculates the address of the instruction to be prefetched from both of them; a prefetch instruction buffer that stores the instruction prefetched according to the address obtained by the calculation; and a CPU. outputs an address signal for reading the next instruction to be executed, the address analysis storage section captures this, and as a result of analysis, it is found that the instruction has already been prefetched and stored in the buffer. When this happens, read this from the buffer and send it to the CPU
An instruction prefetching device comprising: a circuit for supplying an instruction to an instruction prefetching device;