JPS63140493A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To normally input and output a serial access memory SAM even if a spare data register is used by electrically connecting the spare data register to data buses and cutting off a fuse corresponding to a data register to be replaced. CONSTITUTION:When a column composed of a pair of bit lines 7a and 7b and a sense amplifier 8a is replaced with a spare column composed of a pair of bit liens 7g and 7h and a sense amplifier 8d in a RAM part, a cutting fuse 9a is cut off. Thus transistors 14a and 14b are conductive, and the spare data register is connected to the data buses a and 5b. However, since serial gates 6a and 6b remain nonconductive, the data register 1a remained isolated from the data buses 5a and 5b. Thus, the data register 1a is replaced with the spare data register 1d.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a redundant circuit for a serial access memory (hereinafter referred to as SAM).

[Prior Art] In recent years, the applications of dynamic RAM have expanded, and they have come to be used on a large scale in the field of image processing.

Along with this, a so-called dual-port RAM for image processing has appeared. This RAM has an internal RAM section and a SAM section, and is designed to allow mutual data transfer between the RRAM-8A. Also, since the RAM section and SAM section can operate asynchronously, C
Even while the PU accesses the RAM section, the SAM section can continuously input and output image signals, thereby increasing the efficiency of CPU utilization.

FIG. 4 shows, for example, 1986. ICCE Di.

eSt Of l”echnical °pape
RS P, 159 is a diagram showing a connection portion between a RAM section and a SAM section of a conventional dual port RAM published in RS P, 159.

In FIG. 4, data register 1 included in the SAM section
is connected to the sense amplifier 8 of the RAM section via transfer gates 2a and 2b. The sense amplifier 8 has a pit line pair 7a,
It is connected to a memory cell (not shown) via 7b.

Further, the data register 1 of the SAM section is connected to data buses 5a and 5b via serial gates 6a and 6b, and the serial gates 6a and 6h are controlled by the output 4b of the serial selector 3. In addition, outputs 4a and 4c are derived from the serial selector 3.

Note that each column of the RAM section formed by the pit line pair 7a, 7b and the sense amplifier 8 is connected to the transfer gate 2a, 2b.
The serial address of each data register 1 corresponds to the address of each column.

Next, a read operation of the conventional dual port RAM shown in FIG. 4 will be explained. In the RAM section, a word line is selected, data from a memory cell (not shown) is read out to a pair of pin lines 7a and 7b, and then a sense amplifier 8
is amplified by

When the transfer gates 2°a and 2b are turned on at this point, data from the corresponding columns is read into the data register 1.

After that, the serial selector 3 outputs the output signal 4a→4b→4.
Selection signals are sequentially output as shown in C.

For example, when output signal 4b is selected, serial gates 6a and 6b are turned on, and data in data register 1 is read onto data buses 5a and 5b.

In the case of writing, data is written to the selected data register 1 via data buses 5a and 5b, and the data in data register 1 is further transferred to R via transfer gates 2a and 2b.
Written to the AM section.

[Problems to be Solved by the Invention] However, in the conventional dual port RAM described above, the output signal 4a of the serial selector 3.

4b and 4c, the logical order and physical order of each data register 1 must match. For this reason, it is not possible to use a spare data register provided in consideration of chip failure due to contamination with impurities or the like. Also, each data register 1 is connected to each column.
Since it corresponds to one-to-one correspondence, there was a problem in that a spare column could not be used even in the RAM section.

Therefore, the main object of the present invention is to provide a semiconductor memory device in which SAM input/output can be performed normally even when a spare data register is used.

[Means for Solving the Problems] The present invention includes a plurality of data registers arranged in parallel for temporarily storing data, a data bus for data input/output, and a serial selector for sequentially selecting a plurality of data registers, In a semiconductor memory device that is electrically connected to a data bus and capable of inputting and outputting data by selecting a data register, a spare data register is provided to replace the data register, and a serial selector output is connected to the data register via a fuse. A device configured to replace the data register with the spare data register by controlling the connection means, electrically connecting the spare data register and the data bus, and cutting off the fuse corresponding to the data register to be replaced. It is.

[Operation] In the semiconductor memory device according to the present invention, when a data register is selected by the output of the serial selector and the spare data register is made unselected at the same time, and the output of the serial selector is cut by cutting off the fuse, the data register at that position is is not selected and the spare data register remains selected, thereby replacing the data register at that position with the spare data register.

[Embodiment of the Invention] FIG. 1 is an electrical circuit diagram of an embodiment of the invention. First, the configuration will be explained with reference to FIG. The SAM section includes a regular data register 1a.

In addition to 1b and 1C, a spare data register 1d is provided. Note that the transfer gates 2a to 2h,
Serial selector 3, data buses 5a and 5b, serial gates 6a to 6h, and pit line pairs 7a to 7
h and sense amplifiers 8a to 8d are the same as those shown in FIG. 4 described above.

Roughly speaking, outputs 4a, 41) and 4C of serial selector 3 are connected to serial gates 6a and 6b via cutting fuses 9a, 9b and 9C, respectively.

6C and 6d, 6e and 6f, and also connected to the respective gates of transistors 12a, 12b and 12C. Transistors 12a, 12b and 12c are for discharging node 10 for spare column selection, and node 10 is for discharging transistor 1.
Connected to 1. This transistor 11 is node 1
It charges 0.

Further, a transistor 13a is connected to the gates of serial gates 6a and 6b, a transistor 13b is connected to each gate of serial gates 60 and 66, and a transistor 13c is connected to the gates of serial gates 6e and 6f. These transistors 13a, 13b and 13C are for grounding the gates of serial gate controllers a to 6f. Also, spare data register 1d
are connected to serial gates 6a and 6h via transistors 14a and 14b.

FIG. 2 is a timing diagram for explaining the operation of FIG. 7.

Next, with reference to FIG. 1 and FIG. 2, a specific operation of an embodiment of the present invention will be described.

Transistor 11 and transistors 13a to 13
Each gate of transistors 14a and 14b is given an open signal SC as shown in FIG. 2(b), and the transistors 14a and 14b are given an open signal SO as shown in FIG. 2(c). . Also, the serial selector 3 changes the output signal 4a→
They are output sequentially like 4b → 4C. First, a case will be described in which the spare data register 1d is not used.

At time T, the reset signal SC goes to the "H" level, so the transistor 11 becomes conductive and the node 1o is charged to the power supply potential. As a result, serial gates 6g and 6h become conductive. However, the clock signal SO is “
Since the transistors 14a and 14b are in a non-conducting state because of the L'' level, the spare data register 1d
and data buses 5a and 5b are not connected. Also,
Since the transistors 13a to 13C are all turned on by the clock signal SC, the serial gate 6
All of a to 6f become non-conductive. Therefore, all the regular data registers 1a to 1C are also disconnected from the data buses 5a and 5b.

At time T2, the serial selector output 4a is
'' level, transistor 12a and serial gates 6a and 6b become conductive.Thereby, data register 1a and data buses 5a and 5b are connected via serial gates 5a and 5b. That is, data bus 5a.

Data can be input/output to/from data register 1a via 5b. At this time, since the transistor 12a is conductive, the node 10 is discharged, and the serial gate 6g
, 6h become non-conductive, and the spare data register 1d and data buses 5a and 5b are disconnected.

At time T, all data registers 1a to 1d are connected to data bus 5a in the same manner as at time T.
, 5b. Further, at time T4, the serial selector 3 outputs the output signal 4b, so the data register 1b and the data buses 5a and 5b are connected.

Next, the operation when using the spare data register 1d will be explained. In the RAM section, pit line pair 7
Assume that the column consisting of pit line pairs 7g, 7he and sense amplifier 8a is replaced by a spare column consisting of pit line pair 7g, 7he and sense amplifier 8d by a known method. Then, the data to be stored in the data register 1a must be stored in the spare data register 1d. That is, when the serial selector 3 should select the data register 1a, the spare data register 1d must be selected. In this case, the cutting fuse 9a is cut.

Next, the operation when the fuse 9a is cut will be explained. First, at time T, all data registers 1a to 1d are connected to data bus 5a,
5b remains separate.

At time T2, transistor 12a remains non-conductive, so node 10 is not discharged and serial gates 6a and 6h remain conductive. Furthermore, since the clock signal So is at H'' level, the transistor 14a
, 14b becomes one copy, and the spare data register 1d
and data buses 5a and 5b are connected. On the other hand, since serial gates 5a and 5b remain non-conductive, data register 1a and data buses 5a and 5b remain disconnected. In this way, data register 1a and spare data register 1d are replaced.

Also, under the time 3. The operation at time T4 is the same as when fuses 9a to 9C are not cut, and data register 1b is selected at time T4. Similarly,
When replacing the data register 1b with a spare data register 1d, the fuse 9b may be cut, and when replacing the data register 1C with a spare data register 1d, the fuse 9C may be cut.

FIG. 3 is an electrical circuit diagram of another embodiment of the invention. In the embodiment shown in FIG. 1, the fuses 9a to 9C are connected to the output signals 4a to 4c of the serial selector 3, respectively, but in the embodiment shown in FIG. 12a, 12b and 1
Fuses 9a and 9 are connected between 20 and node 10, respectively.
b and 9C are connected. In this case, since the regular data registers 1a to 1c will also be selected, fuses 15 are also connected between each data register 1a to 1C and the serial gates 6a to 6r.
It is necessary to connect the terminals a to 15f to prevent data from the regular data registers from being read onto the data buses 5a and 5b.

Further, in the above embodiment, the case where the present invention is applied to a dual port RAM has been described, but the present invention is not limited to a dual port RAM, and may include a SAM section consisting of a serial selector 3 and data registers 1a to 1C. The present invention can be applied to any case.

[Effects of the Invention] As described above, according to the present invention, when the output of the serial selector reaches the relevant position by cutting the cutting fuse, the spare data register is selected. Therefore, a spare data register can be used for serial access memory.

[Brief explanation of the drawing]

FIG. 1 is an electrical circuit diagram of an embodiment of the present invention. Second
The figure is a timing diagram for explaining the operation of FIG. 1. FIG. 3 is an electrical circuit diagram of another embodiment of the invention. FIG. 4 is an electrical circuit diagram of a conventional dual board t-RAM. In the figure, 1a to 1C are data registers, 1d is a spare data register, 3 is a serial selector, 4a to 4C are serial selector outputs, 5a and 5b are data buses, 9a to 9C and 15a to 15'' are disconnecting fuses, 10 is a spare data register selection node, 11 is a charging transistor, 12a to 120 are discharge transistors, 13a to 13C and 14a,
14b indicates a transistor.

Claims (2)

[Claims] (1) Includes a plurality of data registers arranged in parallel to temporarily store data, a data bus for data input/output, and a serial selector that sequentially selects the plurality of data registers, and one of the plurality of data registers. In a semiconductor memory device that is electrically connected to the data bus and capable of inputting and outputting data by selecting the data bus, a spare data register provided as a replacement for the data register; and a spare data register provided as a replacement for the data register; connection means controlled by the output of the selector and electrically connecting the spare data register and the data bus; and a fuse provided corresponding to each of the data registers and connecting the output of the serial selector and the connection means. 1. A semiconductor memory device comprising: a data register to be replaced with a spare data register by cutting a fuse corresponding to the data register to be replaced. (2) The connection means includes a node that selects the spare data register, a first switching element that charges the node, and a second switching element that is controlled by the output of the serial selector and discharges the node. The semiconductor memory device according to claim 1, comprising: