JPS63139648U - - Google Patents

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Publication number
JPS63139648U
JPS63139648U JP3328787U JP3328787U JPS63139648U JP S63139648 U JPS63139648 U JP S63139648U JP 3328787 U JP3328787 U JP 3328787U JP 3328787 U JP3328787 U JP 3328787U JP S63139648 U JPS63139648 U JP S63139648U
Authority
JP
Japan
Prior art keywords
circuit
name
data
firmware
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3328787U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3328787U priority Critical patent/JPS63139648U/ja
Publication of JPS63139648U publication Critical patent/JPS63139648U/ja
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す流れ図、第2
図はデータ形式を示す説明図、第3図はデータ経
路の例を示す説明図である。 10……データ入力、16……回路名フアイル
、17……フアームウエア制御名フアイル、30
……データ受付回路、31……データ掃出し回路
、35・36……データ経路制御回路、37……
フアームウエアアドレス。
Figure 1 is a flowchart showing one embodiment of the present invention;
The figure is an explanatory diagram showing a data format, and FIG. 3 is an explanatory diagram showing an example of a data path. 10... Data input, 16... Circuit name file, 17... Firmware control name file, 30
...Data reception circuit, 31...Data sweep circuit, 35/36...Data path control circuit, 37...
firmware address.

Claims (1)

【実用新案登録請求の範囲】 データ受付け回路、データ掃出し回路、または
データ経路制御回路の各回路名にそれぞれの接続
先を示す回路名を付けて格納した回路名フアイル
と、 前記データ経路制御回路に含まれるフアームウ
エア制御名にそれぞれの接続先を示すフアームウ
エア制御名およびフアームウエアアドレスを付加
し、前記データ経路制御回路と対応づけて格納し
たフアームウエア制御名フアイルとを有し、 データ受付け回路名およびフアームウエアアド
レスを入力情報として前記回路名フアイルおよび
前記フアームウエア制御名フアイルを順次に索引
し、前記データ受付け回路からデータ掃出し回路
までのデータ経路を決定することを特徴とする不
良データ経路割出し装置。
[Scope of Claim for Utility Model Registration] A circuit name file in which each circuit name of a data reception circuit, data sweep circuit, or data route control circuit is stored with a circuit name indicating each connection destination; A firmware control name and firmware address indicating each connection destination are added to the included firmware control name, and a firmware control name file is stored in association with the data path control circuit, and the data reception circuit name and a firmware address as input information to sequentially index the circuit name file and the firmware control name file to determine a data route from the data acceptance circuit to the data sweep circuit. Device.
JP3328787U 1987-03-06 1987-03-06 Pending JPS63139648U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3328787U JPS63139648U (en) 1987-03-06 1987-03-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3328787U JPS63139648U (en) 1987-03-06 1987-03-06

Publications (1)

Publication Number Publication Date
JPS63139648U true JPS63139648U (en) 1988-09-14

Family

ID=30840761

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3328787U Pending JPS63139648U (en) 1987-03-06 1987-03-06

Country Status (1)

Country Link
JP (1) JPS63139648U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02216541A (en) * 1989-02-17 1990-08-29 Hitachi Ltd Method for generating fault dictionary in device diagnostic supporting system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02216541A (en) * 1989-02-17 1990-08-29 Hitachi Ltd Method for generating fault dictionary in device diagnostic supporting system

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