JPS63138786U - - Google Patents

Info

Publication number
JPS63138786U
JPS63138786U JP3090287U JP3090287U JPS63138786U JP S63138786 U JPS63138786 U JP S63138786U JP 3090287 U JP3090287 U JP 3090287U JP 3090287 U JP3090287 U JP 3090287U JP S63138786 U JPS63138786 U JP S63138786U
Authority
JP
Japan
Prior art keywords
emphasis
video signal
linear pre
linear
changes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3090287U
Other languages
Japanese (ja)
Other versions
JPH0535667Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3090287U priority Critical patent/JPH0535667Y2/ja
Publication of JPS63138786U publication Critical patent/JPS63138786U/ja
Application granted granted Critical
Publication of JPH0535667Y2 publication Critical patent/JPH0535667Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Television Signal Processing For Recording (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図乃至第2図は本考案の一実施例を示すも
のであつて、第1図aはVTRのデイテール・エ
ンフアシス回路における録画側の回路のブロツク
図、第1図bはVTRのデイテール・エンフアシ
ス回路における再生側の回路のブロツク図、第2
図aはノンリニア・プリエンフアシス回路の回路
図、第2図bはノンリニア・デイエンフアシス回
路の回路図、第3図及び第4図は従来例を示し、
第3図はVTRのデイテール・エンフアシス回路
における録画側の回路のブロツク図、第4図はノ
ンリニア・プリエンフアシス回路の回路図である
。 11はノンリニア・プリエンフアシス回路、1
2はAGC電圧増幅器(AGC電圧記録手段)、
13はメイン・プリエンフアシス回路、17は固
定ヘツド(AGC電圧記録手段)、20はノンリ
ニア・デイエンフアシス回路、21はAGC電圧
増幅器、22はメイン・デイエンフアシス回路で
ある。
1 and 2 show an embodiment of the present invention, in which FIG. 1a is a block diagram of the recording side circuit in the VTR's detail emphasis circuit, and FIG. 1b is a block diagram of the VTR's detail emphasis circuit. Block diagram of the playback side circuit in the emphasis circuit, Part 2
Figure a shows a circuit diagram of a non-linear pre-emphasis circuit, Figure 2 b shows a circuit diagram of a non-linear de-emphasis circuit, and Figures 3 and 4 show conventional examples.
FIG. 3 is a block diagram of a recording side circuit in a detail emphasis circuit of a VTR, and FIG. 4 is a circuit diagram of a nonlinear pre-emphasis circuit. 11 is a non-linear pre-emphasis circuit, 1
2 is an AGC voltage amplifier (AGC voltage recording means);
13 is a main pre-emphasis circuit, 17 is a fixed head (AGC voltage recording means), 20 is a non-linear de-emphasis circuit, 21 is an AGC voltage amplifier, and 22 is a main de-emphasis circuit.

Claims (1)

【実用新案登録請求の範囲】 録画の際、映像信号に通常のプリエンフアシス
に加えてノンリニア・プリエンフアシスをかけて
から磁気テープに記録するVTRのデイテール・
エンフアシス回路において、 録画の際に映像信号が受けるノンリニア・プリ
エンフアシス量を当該映像信号を受信したときの
AGC電圧の値により変化させるノンリニア・プ
リエンフアシス回路と、このAGC電圧の値を当
該映像信号と同時に磁気テープに記録するAGC
電圧記録手段と、再生の際に映像信号が受けるノ
ンリニア・デイエンフアシス量を磁気テープから
当該映像信号と同時に読み出したAGC電圧の値
により変化させるノンリニア・デイエンフアシス
回路とを有することを特徴とするVTRのデイテ
ール・エンフアシス回路。
[Scope of Utility Model Registration Claim] VTR detail processing that applies non-linear pre-emphasis to the video signal in addition to normal pre-emphasis before recording it on magnetic tape.
The emphasis circuit includes a non-linear pre-emphasis circuit that changes the amount of non-linear pre-emphasis that a video signal receives during recording depending on the value of the AGC voltage when the video signal is received, and a non-linear pre-emphasis circuit that changes the amount of non-linear pre-emphasis that a video signal receives during recording, and a non-linear pre-emphasis circuit that changes the amount of non-linear pre-emphasis that a video signal receives during recording, and a non-linear pre-emphasis circuit that changes the amount of non-linear pre-emphasis that a video signal receives during recording. AGC recorded on tape
A detail of a VTR characterized by having a voltage recording means and a non-linear de-emphasis circuit that changes the amount of non-linear de-emphasis that a video signal receives during playback according to the value of an AGC voltage read out from a magnetic tape at the same time as the video signal. -Emphasis circuit.
JP3090287U 1987-03-03 1987-03-03 Expired - Lifetime JPH0535667Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3090287U JPH0535667Y2 (en) 1987-03-03 1987-03-03

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3090287U JPH0535667Y2 (en) 1987-03-03 1987-03-03

Publications (2)

Publication Number Publication Date
JPS63138786U true JPS63138786U (en) 1988-09-13
JPH0535667Y2 JPH0535667Y2 (en) 1993-09-09

Family

ID=30836137

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3090287U Expired - Lifetime JPH0535667Y2 (en) 1987-03-03 1987-03-03

Country Status (1)

Country Link
JP (1) JPH0535667Y2 (en)

Also Published As

Publication number Publication date
JPH0535667Y2 (en) 1993-09-09

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