JPS63138582U - - Google Patents
Info
- Publication number
- JPS63138582U JPS63138582U JP3062387U JP3062387U JPS63138582U JP S63138582 U JPS63138582 U JP S63138582U JP 3062387 U JP3062387 U JP 3062387U JP 3062387 U JP3062387 U JP 3062387U JP S63138582 U JPS63138582 U JP S63138582U
- Authority
- JP
- Japan
- Prior art keywords
- month
- calendar
- displayed
- predetermined period
- discriminating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- RRLHMJHRFMHVNM-BQVXCWBNSA-N [(2s,3r,6r)-6-[5-[5-hydroxy-3-(4-hydroxyphenyl)-4-oxochromen-7-yl]oxypentoxy]-2-methyl-3,6-dihydro-2h-pyran-3-yl] acetate Chemical compound C1=C[C@@H](OC(C)=O)[C@H](C)O[C@H]1OCCCCCOC1=CC(O)=C2C(=O)C(C=3C=CC(O)=CC=3)=COC2=C1 RRLHMJHRFMHVNM-BQVXCWBNSA-N 0.000 description 1
Landscapes
- Electric Clocks (AREA)
Description
第1図は、本考案の一実施例の回路構成を示す
ブロツク図、第2図aは、表示部2の外観図、第
2図bは、表示部2のカレンダ表示部21の拡大
図、第3図は、RAM5の主要部の構成図、第4
図は、本実施例のシステム全体の動作を示すゼネ
ラル・フロー、第5図、第6図は、キー処理の動
作を示すフローチヤート、第7図、第8図は、本
実施例の表示動作を示す図。
2……表示部、2a……表示バツフア、3……
ROM、4……ROMアドレス制御部、5……R
AM、6……インストラクシヨンデコーダ、7…
…演算回路、9……発振器、11……キー入力部
、12……分周回路、CMEM……カレンダメモ
リ領域、L,M……モードフラグ、N……カレン
ダメモ許可フラグ、P……カレンダメモ設定フラ
グ、Y1〜Y3……ポインタ、S1〜S4……キ
ー。
1 is a block diagram showing the circuit configuration of an embodiment of the present invention, FIG. 2a is an external view of the display section 2, and FIG. 2b is an enlarged view of the calendar display section 21 of the display section 2. Figure 3 is a configuration diagram of the main parts of RAM5.
The figure shows a general flow chart showing the operation of the entire system of this embodiment. Figures 5 and 6 are flowcharts showing the key processing operation. Figures 7 and 8 show the display operation of this embodiment. Diagram showing. 2...display section, 2a...display buffer, 3...
ROM, 4...ROM address control section, 5...R
AM, 6...Instruction decoder, 7...
... Arithmetic circuit, 9 ... Oscillator, 11 ... Key input section, 12 ... Frequency division circuit, CMEM ... Calendar memory area, L, M ... Mode flag, N ... Calendar memo permission flag, P ... Calendar Memo setting flag, Y1 to Y3 ...pointer, S1 to S4 ...key.
Claims (1)
段と、 日付データを入力する入力手段と、 カレンダ表示が行なわれる月が、前記計時手段
の計数する現在の日付から所定期間内であるか否
かを判別する判別手段と、 この判別手段によりカレンダ表示の月が所定期
間内であると判別された場合にはその旨を表示す
る表示手段と、 前記判別手段によりカレンダ表示の月が所定期
間内であると判別された場合のみ、前記入力手段
により入力された日付データを記憶する記憶手段
とを具備することを特徴とするカレンダ表示装置
。[Scope of Claim for Utility Model Registration] At least a clock means for counting the current year, month, and day, an input means for inputting date data, and a month in which a calendar is displayed is from the current date counted by the clock means. a discriminating means for discriminating whether or not the month on the calendar is within the predetermined period; a display means for displaying a message to that effect when the discriminating means determines that the month displayed on the calendar is within the predetermined period; A calendar display device comprising: storage means for storing date data input by the input means only when it is determined that the displayed month is within a predetermined period.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3062387U JPS63138582U (en) | 1987-03-03 | 1987-03-03 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3062387U JPS63138582U (en) | 1987-03-03 | 1987-03-03 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63138582U true JPS63138582U (en) | 1988-09-12 |
Family
ID=30835605
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3062387U Pending JPS63138582U (en) | 1987-03-03 | 1987-03-03 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63138582U (en) |
-
1987
- 1987-03-03 JP JP3062387U patent/JPS63138582U/ja active Pending
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