JPS63137955U - - Google Patents

Info

Publication number
JPS63137955U
JPS63137955U JP1987028780U JP2878087U JPS63137955U JP S63137955 U JPS63137955 U JP S63137955U JP 1987028780 U JP1987028780 U JP 1987028780U JP 2878087 U JP2878087 U JP 2878087U JP S63137955 U JPS63137955 U JP S63137955U
Authority
JP
Japan
Prior art keywords
semiconductor chip
mounting table
lead frame
hole
wire connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987028780U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987028780U priority Critical patent/JPS63137955U/ja
Publication of JPS63137955U publication Critical patent/JPS63137955U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Die Bonding (AREA)
JP1987028780U 1987-03-02 1987-03-02 Pending JPS63137955U (pt)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987028780U JPS63137955U (pt) 1987-03-02 1987-03-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987028780U JPS63137955U (pt) 1987-03-02 1987-03-02

Publications (1)

Publication Number Publication Date
JPS63137955U true JPS63137955U (pt) 1988-09-12

Family

ID=30832058

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987028780U Pending JPS63137955U (pt) 1987-03-02 1987-03-02

Country Status (1)

Country Link
JP (1) JPS63137955U (pt)

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