JPS63136232A - Information processor - Google Patents

Abstract

PURPOSE:To improve the performance of an arithmetic processing part up to a 100%-level by inputting a data packed after allocating it to plural program memory parts and providing the routes for individual connection between each program memory part and a paired data detecting part. CONSTITUTION:An allocating part 25 allocates the data packet outputted from an arithmetic processing part 24 to two program memory parts 21 and 22. Thus both parts 21 and 22 receive inputs with 1/2 rate of the maximum performance. If the parallel processing programs are executed, the parts 21 and 22 perform data copies 40 and 41 respectively and the flow rates of two routes 26 and 27 are set a '1' respectively. Thus the flow rate '1' is attained with an output route 28 since a paired data detecting part 23 receives input of the flow rate '1' from both inputs. In other words, the maximum performance of the flow rate is secured up to a route 29. Therefore the performance of the part 24 can be improved up to a 100%-level and the parallel processing effect doubled.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention executes a program including instructions for performing arithmetic processing using two sets of data, such as general numerical arithmetic and logical arithmetic processing. Related to Information Processing Apparatus <Prior Art> FIG. 2 shows a block diagram of a conventional information processing apparatus. Furthermore, FIG. 3 shows the field structure of a data packet in the same device.

In the figure, 1 stores a data flow program, uses the contents of the destination field of the input data packet (destination light information) as an address, reads out the destination light information and command information, and transfers each piece of information to the destination of the input data packet. This is a program storage unit that stores and outputs data in fields and instruction fields. 2 waits for data packets input from the program storage unit 1 (detects two data packets with matching outgoing optical information), and detects one of the two data packets with matching outgoing optical information. Operand data (contents of data 1 field)
This is a paired data detection unit that stores and outputs the data in the data 2 field of the other data packet. Note that at this time, one of the data packets mentioned above disappears. 3 decodes the command information of the data packet input from the paired data detection unit 2;
This is an arithmetic processing section that performs predetermined arithmetic processing on the two operand data, stores the result in the data 1 field of the input data packet, and outputs it to the program storage section t section 1. Note that 4 is a path connecting the program storage section 1 and the paired data detection section 2. The reason why the path 4 branches here is to schematically represent the two left and right inputs for the calculation, as shown in FIG. Also, 5
is a path connecting the paired data detection section 2 and the arithmetic processing section 3.

Further, 6 is a path connecting the arithmetic processing section 3 and the program storage section 1.

As the data packet continues to circulate between the program storage section 1, the data detection section 2, the arithmetic processing section 3, the program storage section 1, and so on, the arithmetic processing based on the program stored in the program storage section 1 progresses.

Now, consider the case where the program shown in FIG. 5 is executed.

This is an example of a parallel processing program in which two operations 11 and 12 are placed in parallel. First, the data entered in 10 needs to proceed to two operations, 11 and 12. For this purpose, data must be copied. That is, the data in this case is not generated from outside the processing device, but is generated internally. Specifically, the copy process is performed in the program storage unit 1. FIG. 6 is a diagram showing a part of the contents stored in the program storage unit.

Copy presence/absence information is stored in the forward light information and command information pools. The contents of the portion addressed based on the forward light information of the input data packet are first read. At this time, if the copy presence/absence information is "None", a data packet with updated contents of the destination field and instruction field is output and the process ends.
If the no information is "present", a data packet with updated contents of the destination field and command field is output, and the stored destination light information, command information, and copy presence/absence information are subsequently read out. . I have a copy of this/
If no information is "none", the contents of the data 1 field are the same as the input data packet, the data packet in which the information that has just been read is stored is output to the destination field and the command field, and the process ends. do. That is,
Copy processing is executed. If the copy presence/absence information is “yes”, copy processing is further performed.

<Problems to be Solved by the Invention> Assuming that data copying is performed once (two copy instructions are executed), the input path 6 to the program storage unit 1
and the flow rate ratio of the output path 4 is always 1:2. Therefore, even if route 4 operates at maximum performance, the data detection unit 2 outputs one data packet for each two data packets input, so routes 5 and onwards will operate at half the maximum performance. Only flow rate is guaranteed. FIG. 7 shows the flow rate.

Paths 5 and 6 thus operate at only one-half of their maximum performance. As a result, the performance of the arithmetic processing section 3 is reduced to only one-half, resulting in an impediment to the performance of the information processing device.

The present invention aims to solve the above-mentioned problems in conventional devices.〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇〇　Means for solving the problems〉>> is provided in which a plurality of program storage units are provided and data packets are outputted from an arithmetic processing unit. is distributed and input to the plurality of program storage sections, and a plurality of paths are provided that individually connect each program storage section and the paired data detection section.

<Example> Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a block diagram of one embodiment of the present invention.

This embodiment is provided with two program storage sections. In other words, the program storage section is duplicated.

In the figure, 21 and 22 are program storage units, 23 is a paired data detection unit, and 24 is an arithmetic processing unit.

The functions of these parts are exactly the same as those of the conventional device.

That is, a feature of this device is that it does not require addition of special functions inside each functional section.

Furthermore, the field configuration of the data packet is also exactly the same as that of the conventional device.

Reference numeral 25 denotes a distribution section for distributing data packets output from the arithmetic processing section 24 to two program storage sections 21 and 22. Its configuration is shown in FIG. In the figure, 251 is a branch control section, 252 is a branch section, and the branch control section 251 outputs an output route switching signal to the branch section 252 every time a data packet is input. As a result, the first data packet is output to the upper output path, the second data packet to the lower output path, the third data packet to the upper output path, and so on. It will be done.

26 is a path connecting the program storage section 21 and the paired data detection section 23, and 27 is a path connecting the program storage section 22 and the paired data detection section 23. Further, 28 is a path connecting the paired data detection section 23 and the arithmetic processing section 24. Furthermore, (, 29 is a path connecting the arithmetic processing section 24 and the distribution section 25, 30 is a path connecting the distribution section 25 and the program storage section 2
1, and 31 is a path connecting the distribution section 25 and the program storage section 22.

In this device, since the distribution section 25 distributes the inputs to the program storage sections 21 and 22, inputs are input to both the program storage sections 21 and 22 at a rate of 1/2 of the maximum performance. Here, when the parallel processing program shown in FIG. 9 is executed, 40 data copies are stored in the program storage unit 21.
However, if the program storage unit 22 performs 41 data copies, the flow rate of each of the paths 26 and 27 becomes 1. Therefore, since the paired data detection unit 23 receives input of a flow rate of 1 from each of the two human forces, a flow rate of 1 can be achieved in the output path 28. In other words, the highest performance flow rate is ensured up to the path 29. Figure 10 shows the flow rate.

Therefore, the performance of the arithmetic processing unit can be increased to 100%, and the effect of parallel processing is twice that of the conventional device.

This concludes the description of the first embodiment.

Next, a second embodiment of the present invention will be described.

FIG. 11 is a block diagram of the second embodiment.

Furthermore, the field structure of the data packet in the same device is shown in FIG. The performance of the arithmetic processing unit will not deteriorate even when a program including the above is executed.

In the figure, 51, 52 and 53 are program storage units.

FIG. 14 shows a part of the contents stored in the program storage section.

The program storage units 51, 52 and 53 store a data flow program, read the contents of the destination field of the input data packet (as the destination light information>1 address, and read the destination light information, command information, and tag information, and store the respective information as described above). It is stored in the destination field, command field, and tag field of the input data packet and output.The tag information will be described later.

54 waits for data packets input from the program storage unit 51, 52, 53, and reads the operand data (contents of data 1 field) of one of the two data packets whose forward optical information matches. This is a paired data detection unit that stores and outputs the data in the data 2 field of the other data packet. Note that at this time, one of the data packets mentioned above disappears. The data detection unit 54! g1 pair data detection unit 541 and second pair data detection unit 54
2, further includes a data packet branching section 543 and a data packet merging section 544. The tag information is information indicating which number of the first paired data detection section 541 and the second paired data detection section 542 the data packet should be waited for. If it is “0”, the first paired data detection unit 541 performs the waiting, and if it is “1”, the second paired data detection unit 542 performs the waiting.

The configuration of the data packet branching section 543 is shown in FIG.

The branch control unit 545 determines that the tag information of the input data packet is “
0'', a branch signal is output to the branch unit 546. As a result, the input data packet is input to the merging section 544.

When the tag information is “1”, no branch signal is output, and the data packet is input to the second paired data detection unit 542.

The configuration of the data packet merging section 544 is shown in FIG.

When the vacancy determining unit 547 detects that there is a vacancy, the merging unit 548 operates and the data packet branching unit 54
The data packets input from 3 are merged.

The first pair data detection unit 541 advances pair detection to 1 when the tag information of the input data packet is "0",
]°1”, it is simply passed through.

In addition, the second paired data detection unit 542 simply passes the input data packet depending on the tag information of the input data packet when it is “0”, and proceeds to pair detection when it is “1”. 54, performs predetermined arithmetic processing on the two operand data, stores the result in the data 1 field of the input data packet, and outputs the result. .

56 is a distribution section for distributing data packets output from the arithmetic processing section 55 to three program storage sections 51, 52, and 53. Its configuration is shown in FIG.

The branch control unit 561 controls the branch unit 56 for each data packet input.
An output route switching signal is output to 2. This causes the first data packet to go to the top output path, the second data packet to the middle output path, the third data packet to the bottom output path, and the fourth data packet to the top output path. , , etc. 057 is a path connecting the program storage section 51 and the paired data detection section 54 , 58 is a path connecting the program storage section 52 and the paired data detection section 5
4, and 59 is a path connecting the program storage section 53 and the paired data detection section 54. Further, 60 is a path connecting the paired data detection section 54 and the arithmetic processing section 55. Furthermore, 61 (is arithmetic processing unit 55 and shooting division unit 56
Paths 62, 63, and 64 are paths that connect the distribution section 56 and the program storage section 51, program storage section 52, and program storage section 53, respectively.

Based on the same idea, it is also possible to configure an information processing device in which the number of program storage units is further increased. <Effects of the Invention> As explained in detail above, according to the present invention, the performance of the arithmetic processing unit can be improved. Accordingly, it is possible to obtain an extremely useful information processing device that is not hindered and whose performance can be improved compared to the conventional one.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a block diagram of a conventional information processing device, FIG. 3 is a field configuration diagram of a data packet in the same device, and FIG. 4 is a block diagram of a conventional information processing device. +
Figure 5 is a diagram showing a part of a program in which several operations are written in parallel, and Figure 6 is a diagram illustrating a program that uses two people and one output to perform the above-mentioned conventional device. FIG. 7 is a diagram showing the flow rate of each path constituting the device, FIG. 8 is a block diagram of the distribution section constituting the first embodiment of the present invention, and FIG. 9
Figure 10 is a diagram showing an example of a program with parallel calculations, Figure 10 is a diagram showing the flow rate of each route constituting the first embodiment, and Figure 11 is a block diagram of the second embodiment of the present invention. figure,
FIG. 12 is a field configuration diagram of a data packet in the same embodiment, FIG. 13 is a diagram showing an example of a program with parallel operations, and FIG. 14 is a diagram showing the program storage unit constituting the second embodiment. Diagram showing part of the memory contents in 1st
FIG. 5 is a block diagram of a data packet branching section provided inside the paired data detection section that constitutes the same embodiment, FIG. 16 is a block diagram of the data packet merging section, and FIG. 17 is a distribution section that constitutes the same embodiment. FIG. Explanation of symbols 21. 22 Niprogram storage unit, 23: Pair data detection unit, 24: Arithmetic processing unit, 25: Distribution unit,
2+3.27, 28, 29, 30, 31: route, 51
．． 52, 53 Niprogram storage unit, 54: paired data detection unit, 55; arithmetic processing unit, 56: distribution unit, 57
, 58, 59, 60° 61. 62, 63, 64: Route. Agent Patent attorney Takeshi Sugiyama (and 1 other person) Hiroshi 9
. 4 1st rjA 2nd Figure $3 Figure 5 Figure 6 Figure 7 Figure 8 Figure 91jA Figure 11 Figure 14

Claims (1)

[Claims] 1. Store a data flow program, use the contents of the destination field (destination light information) of the input data packet as an address, read out the destination light information and command information, and read out the destination light information and command information, and use the respective information in the input data packet. a program storage unit that stores and outputs the destination field and the instruction field;
A pair that waits for data packets input from the program storage unit, stores operand data of one of the two data packets with matching optical information in the data field of the other data packet, and outputs the data packet. The data detection unit decodes the instruction information of the data packet input from the paired data detection unit, performs predetermined arithmetic processing on the two operand data, and stores the result in the data field of the input data packet. and an arithmetic processing unit that outputs data to the program storage unit, wherein the program storage unit has a copy function, that is, creates and outputs one or more data packets having the same input data packet and operand data. In an information processing device having the above-mentioned function, a plurality (N) of the above-mentioned program storage sections, a distribution means for distributing and inputting data packets output from the above-mentioned arithmetic processing section to the above-mentioned plurality of program storage sections; An information processing device characterized by providing a plurality (N) of paths connecting each program storage section and the paired data detection section.