JPS63136223A - Hash circuit - Google Patents

Abstract

PURPOSE:To shorten the processing time and to simplify the constitution of a has circuit by outputting the intermediate hash value having the satisfactory random properties to the value of the input partial data and integrating the intermediate hash values stored in a table and corresponding to each partial data. CONSTITUTION:The contents of tables 130, 140 and 150 holding the intermediate hash values are read out by setting the value of input data to an address register 90. The intermediate hash value having the satisfactory random properties to all values of the input partial data is calculated and stored previously into each of said tables. The input is divided into high-order bits and low-order M/2 bits with the length of an output register 100 set at N bits. The high-order M/2 bits of the register 90 are used as the address of the table 130. Then the contents of the table 130 and the low-order M/2 bits of the register 90 are used as addresses to read out the tables 140 and 150. The hash values of each table are integrated by an integrating circuit 110 and the result of this integration is set at the register 100 for acquisition of the hash value.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hash circuit used in a data management system using an information processing device.

[Prior Art] Conventionally, various hash functions for hash circuits have been proposed, including division methods, multiplication methods, basic conversion methods,
There are algebraic encoding methods, and furthermore, there are integration methods such as the superposition method and folding method.

The division method considers the internal code of the data as a binary value, and M
This method uses the remainder after dividing by an integer (actually the size of the hash table) as the hash address.

The multiplication method is a method in which data is multiplied by itself or by a certain constant, and only the required number of bits are extracted from around the center of the resulting bit string according to the hash table size.

The basic conversion method is to consider the data as a p-adic number string, convert it to a q-adic number, and extract the necessary number of bits from the number string (the conversion operation is a repetition of division).
.

The algebraic encoding method is similar in concept to the division method, and instead of dividing by an integer, remainder calculation is performed using a polynomial expression.

The superposition method divides data into certain units and performs addition, exclusive OR (EXOR), etc. for each division, while the folding method performs calculations to fold each of the above divisions.

In addition, as a known document explaining the hash function, for example, "Journal of the Institute of Electronics and Communication Engineers J (Vol. 63° No.
pp. 20-26.1980) by Toshitsugu Yumiba, “Hashing-based heading search technique [n]” and “Information Processing J.
(VOl, 21.NO, 9°pp, 980-991.
Examples include ``Hashing Techniques and Applications'' by Kiyoshi Nishihara (1980).

[Problems to be Solved by the Invention] If the above-mentioned division method, multiplication method, basic conversion method, and algebraic encoding method are implemented using circuits corresponding to each operation, the circuit becomes complicated and the hardware scale increases. There are problems in that the size of the hash value increases and the processing time required to obtain the hash value is long.

An object of the present invention is to provide a hash circuit which can shorten processing time until obtaining a hash value.

[Means and effects for solving the problem] In the present invention, input data is divided into several sections with fixed lengths (
This intercept is called partial data). In advance, calculate a hash value with good randomness (intermediate hash value) for all (input) values of the partial data, create a table to store it, and then When inputting , it outputs intermediate hash values with good randomness for the input partial data values, and then integrates the intermediate hash values corresponding to each partial data (intercept), which is repeated until the data is finished. The feature is that the hash value is obtained.

[Example] FIG. 1 is a diagram showing a first example of the present invention, and is an example in which data is divided into only one section.

120 is a table that holds hash values created on the RAM or ROM, 9o is an address register that addresses the table 120, and 100 is a register that sets the contents read from the table 120.

Here, it is assumed that converted values with good randomness are calculated for all values of input data in advance, and a table is created in which the converted values (hash values) are stored. A specific example of a converted value is storing the multiplication result of the input data value and a constant in the multiplication method, but it is not limited to this, and it is possible to store converted values with good randomness as a table. Any method may be used as long as it outputs the output.

Here, the length of the address register 90 is M (arbitrary integer) bits, and the length of the output register 100 is assumed to be N (arbitrary integer) bits.

By setting the value of input data in the address register 90, the contents of the table 120 are read out and set in the output register 100 to obtain a hash value.

FIG. 2 is a diagram showing a second embodiment of the present invention, 11
0 is addition (ADD) or exclusive OR (EXOR)
130, 140, 150 is a table that holds intermediate hash values.

By setting the value of input data in the address register 90, a table 130, 1 that holds intermediate hash values is set.
Read the contents of 40,150.

Here, it is assumed that the tables 130, 140, and 150 calculate intermediate hash values with good randomness for all values of input partial data in advance and store them. Any method may be used as the table as long as it outputs intermediate hash values with good randomness.

Here, the input data length is M bits, and is divided into segments (partial data) with a fixed length of M/2 bits, and the address register 90 that holds the data is divided into upper M/2 bits, lower M/2 bits, and It is divided into two parts of 2 bits, and the table will be explained using three cases. Also, the length of the output register 100 is N
Bit.

The contents of the table 130 are set as the address of the table 130 using the second position M/2 BiSoto of the address register 90.
Further, the tables 140 and 150 are read using the lower M/2 bits of the address register 90 as an address. Next, the output contents of tables i3o and i40.150 (each intermediate hash value) are integrated by the integration circuit 110,
The result is set in the output register 100 to obtain a hash value.

FIG. 3 is a diagram showing a third embodiment of the present invention, in which when the length of input data is long, integration corresponding to each partial data is performed in multiple stages based on the method shown in FIG. It is something to do. The input data shall be divided into multiple sections with fixed lengths.

Alternatively, a table hashing machine having the configuration shown in Fig. 2, 1
Reference numeral 60 denotes an integration circuit that integrates the output contents of the table hash unit for each partial data (intercept). In the integrated circuit 160, 30 is a hash register that holds a hash value or an intermediate hash value, and 50 is a hash register that performs a specific operation (addition or exclusive OR) on the output contents of the table hash unit and the output contents of the hash register. 60 is a rotation circuit that rotates all the contents of the hash register by a specified number of bits, and 70 indicates the number of bits to be rotated by the rotation circuit 60. This is the input terminal for the signal to be output.

The operation of FIG. 3 is as follows. Here, the data length is M
The length of the partial data is explained as l (any integer) bytes, and the length of the partial data is m (any integer) bytes.

The table hash unit 40 uses the value of the partial data (length m bytes) as an address (stored in the address register 90 in FIG. 1 or 2), and reads out the contents of the table as an intermediate hash value or an intermediate hash Outputs a value after performing a simple operation.

Next, the integration circuit 160 sequentially integrates the output contents of the table hash unit for each partial data (intercept), and is the integration circuit 110 shown in FIG. 2 with a rotation circuit added thereto. The operation of integrated circuit 160 will be explained.

The rotation circuit 60 rotates all the bits of the hash register by the number of bits in accordance with a signal (input from the terminal 70) indicating the number of bits to be rotated. (The number of bits to rotate is determined based on the input data format (binary data format, character string data format, etc.), maximum value (or maximum length), hash table size, etc.) Next, the superposition circuit 50
A specific operation (such as an addition or an exclusive OR (EXOR) operation) is performed on the output contents of the rotate circuit 60 and the output contents of the rotate circuit 60, and the result is written back to the hash register 30. (The hash register 30 is cleared each time one data hash has been completed.) The above-mentioned process is repeated for all the partial data (until the data is completed) to obtain the hash value, and the hash address is Output to the output terminal 80.

Here, the integrated circuit may use a simple operation such as addition or exclusive OR (EXOR), or it can be easily configured by using a method such as superposition or folding.

Note that the means of integration is not limited to this,
Any method is fine as long as it can be integrated.

Furthermore, the length of the input data and the hash value (length of the hash address) can be easily configured to any length. Furthermore, even if the data division method (fixed/variable number, section length, etc.) and the number of tables are arbitrary, the structure can be easily configured by changing the integration method.

Furthermore, it is also possible to easily configure a case where input data is divided into segments of fixed length and inputted in a stream format with the byte width of the partial data.

[Effects of the Invention] As explained above, according to the present invention, by using a hash circuit using one table or a plurality of tables and a simple integration means, (1) randomness can be reduced for input data values; Output a good conversion value and use it as a hash value, or (2) Divide the input data into multiple intercepts with a fixed length and perform a conversion with good randomness for all values of the partial data. Output the value (intermediate hash value), and then integrate the output contents of the table for each partial data (intercept), which is repeated for all partial data (until the data is finished) to obtain the hash value. Therefore, there are advantages in that the circuit configuration is simplified, the hardware scale can be reduced, and the processing time required to obtain a hash value can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a block diagram of a second embodiment of the present invention, and FIG. 3 is a block diagram of a third embodiment of the present invention. 20... Input register, 30... Hash register, 40... Table hash unit, 50... Superposition circuit, 60... Rotate circuit, 80... Hash address output terminal, 90...address register,
100...Output register, 110.160...Integrated circuit, 120,130,140.150...Table. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] It is characterized by comprising a table into which data divided into one or more sections is input and holds an intermediate hash value corresponding to the value of the section, and means for integrating read contents of the table corresponding to each section. hash circuit.