JPS6313473A - Horizontal synchronizing signal reproducing circuit - Google Patents

Abstract

PURPOSE:To suppress the occurence of horizontal jitters or horizontal lateral disorder of picture in VTR reproduction mode by controlling the loop gain or the filter characteristic of a horizontal AFC circuit by a detection voltage in a level corresponding to the state of noise in a composite video signal. CONSTITUTION:A horizontal synchronizing signal pulse HP outputted to the collector-side of a horizontal synchronizing separator 12 is inputted to a phase detection circuit 14. This horizontal synchronizing signal pulse HP is impressed to a transistor Q9 connected in a differential connection, and to the emitter of this transistor Q9 is the emitter of a transistor Q15 for phase detection current control connected. When the number of differential signal to be inputted is increased, the transistor Q15 reduces the output current of the phase detection circuit 14 to reduces the loop gain of the horizontal AFC circuit. On the other hand, if a horizontal synchronizing signal pulse is separated without being disoredered by noise, the phase detection current is made large i.e. the loop gain is maintained large. In such a way, horizontal jitters in the weak electric field and the horizontal disorder, etc. of a picture in the VTR reproduction mode can be suppressed.

Description

Detailed Description of the Invention [Objective of the Invention] (Industrial Application Field) The present invention is based on the state of the horizontal synchronizing signal separated from the composite video signal, and the loop gain etc. of the horizontal AFC circuit are input to the composite video signal. The present invention relates to a horizontal periodic signal reproducing circuit equipped with means for controlling a value to a value suitable for a video signal.

(Prior Art) Conventionally, a preview receiver (hereinafter referred to as a TV receiver) receives input composite video signals from an input composite video signal. The image is faithfully displayed on the display screen by means of a deflection signal synchronized with this synchronization signal.

The deflection circuit that generates the deflection signal compares the phase with the synchronization signal separated from the composite video signal, and uses a horizontal automatic frequency control circuit (hereinafter referred to as horizontal AFC circuit) to generate a deflection signal synchronized with the synchronization signal. ).

In conventional horizontal AFC circuits, horizontal jitter occurs in weak electric field areas when receiving TV signals, and video tape recorders (
Hereinafter, it will be referred to as VTR. ) When reproducing the recorded signal, there was a problem in that horizontal lateral wobbling and bending occurred.

The horizontal A'FC circuit of a conventional TV receiver (!(In) employs a PLL type control system as shown in FIG.

That is, a synchronization signal is separated and extracted from the composite video signal by a synchronization separation circuit 1, and this synchronization signal is input to a phase detection circuit 2.
The phase is compared with the horizontal oscillator 3, and a comparison signal is output. A signal component on the low frequency side of this comparison signal is extracted through a filter circuit 4, and this signal component on the low frequency side is applied to the horizontal oscillator 3 to synchronize the horizontal oscillation signal of the horizontal oscillator 3 with the synchronization signal.

By the way, in the above PLL type i+l control system, the oscillation frequency is changed according to the phase difference between the horizontal synchronization signal and the horizontal deflection output pulse, and the unit phase difference ( In other words, the amount of change with respect to 1 radian) is expressed as a loop gain. This PL
When the L-type control system is used, the optimum values of the loop gain and the filter characteristics of the filter circuit 4 suppress the jitter that occurs in the TV signal input mode and the horizontal lateral vibration and bending that occur in the VTR signal input mode. The optimal m for is completely different. For this reason, in most conventional TV receiver designs, circuit constants are set to suppress these two factors to some extent.

Also, with some TV receivers, the VTRTR signal is
There are some that switch between mode and TV signal reception mode, and others whose characteristics can be changed using a service switch.

In other words, in areas where the amplitude of the TV signal is small, such as in weak electric field areas, the composite video signal is disturbed by noise, and the horizontal synchronization signal separated from the normal one shown in Figure 6 (a) changes from the normal one shown in Figure 6 (a) to the one shown in Figure 6 (b). It becomes disordered as shown in the figure. For this reason,
When the PLL loop is operated to follow the phase of this synchronization signal, the deflection frequency of the horizontal oscillator also becomes unstable, resulting in horizontal jitter on the screen.

By the way, if the frequency of the horizontal synchronizing signal part of the video signal being transmitted is accurate and stable (not subjected to FM modulation, etc.) as in the TV reception mode, go to F.
Once the C loop is locked, the loop gain of the PLL loop is not so necessary, and it is desirable to keep the loop gain low in order to keep the reproduction of the horizontal synchronization signal from being disturbed by disturbance noise.

On the other hand, in the video signal in VTR signal input mode,
Since the video signal is FM-modulated due to the expansion and contraction of the data wave peculiar to VTRs, the horizontal synchronization in this FM-modulated video signal is different from the normal horizontal synchronization signal shown in Figure 7(a). The signals are shifted in time as shown in FIG. 3(b). For this reason, if the loop gain of the PLL loop is low, it becomes difficult to accurately synchronize and reproduce this FM-modulated video signal, causing horizontal shaking or bending of the screen. In other words, in the VTR signal input mode, it is desirable that the loop gain of the horizontal AFC circuit be high.

In this way, it is necessary to have a somewhat large loop gain and filter characteristics when in the VTR signal input mode, while a low loop gain is required when in the TV signal reception mode in areas with poor radio wave conditions such as weak electric field areas. be done.

(Problems to be Solved by the Invention) In the conventional example in which the horizontal AFC loop gain and filter characteristics are switched between the VTR input mode and the TV signal reception mode, the video input is performed only during VTR video playback. However, when a TV signal is received using a tuner on the VTR side, synchronized playback must be performed with a high loop gain, which is not preferable.

In addition, regarding the method of changing the filter characteristics using a Levis switch, the general value is T V , /
It is better to change the V T fl by changing the switch (it is more erratic and inconvenient).

SUMMARY OF THE INVENTION An object of the present invention is to provide a horizontal periodic signal regeneration circuit which eliminates the above-mentioned drawbacks and which can automatically set the loop gain or filter characteristics suitable for image reception.

[Structure of the invention] - (P stage for solving problems) In the horizontal open 1111 signal reproducing circuit of the present invention, horizontal synchronization No. a differentiating circuit that differentiates the synchronization signal; a detection circuit that detects the differentiated signal to obtain a detected voltage at a level corresponding to the noise state of the input composite video signal;
A ΔFC control circuit is provided which controls the loop gain or filter characteristics of the horizontal AFC circuit using this detected voltage.

(Function) In the horizontally open No. During regeneration, the detection voltage becomes low. This detection voltage is used to control the oscillation frequency of the horizontal oscillation circuit forming the horizontal automatic frequency control circuit, and when there is a lot of disturbance due to noise, the t and L oscillation frequencies The control function is small, and on the other hand, when there is a normal TM01 or VTR playback signal, the control function is 1.
The function is too large to suppress the occurrence of horizontal jitter.
This suppresses horizontal and lateral vibrations in R playback mode.

(Example) 1. Examples shown in the drawings below. ! Next, the present invention will be explained in detail.

FIG. 1 does not show the horizontal periodic signal reproducing circuit 11 of one embodiment of the present invention (91).

This horizontal periodic signal reproducing circuit 11 (a horizontal synchronization division 1 circuit 12 that separates the horizontal open 1! II f, j pulse HP from the input composite video signal 3cv, and The horizontal oscillation pulse that has passed through the flyback transformer 13 of the IP and water/dust oscillation output circuit is converted into a sawtooth wave and inputted to the phase detection circuit 14, and the comparison signal whose phase has been compared in this phase detection circuit 14 is sent to the filter circuit 15. The horizontal periodic signal reproducing circuit 11 is connected to the horizontal oscillation circuit 16 which is inputted as a horizontal AFC signal through the horizontal AFC signal.
7 and this differential legend is LS i%! The waveform is shaped by comparing the voltage with the voltage, and this waveform-shaped output signal is used to generate II! (The waveform shaping detection circuit 18 generates a detection type J-[ corresponding to the number of three differential signals input per Q time.

The above composite video signal "; FiSCv is applied to the base of the transistor Q1 via the resistor R1 and the direct IJIJ circuit of capacitors IJ-CI. When connected, it is grounded via the resistor R2.The emitter of the transistor Q1 is also connected to the power supply terminal Vcc, and the jitter is grounded via the series circuit of the resistors R3 and R4. Therefore, resistors R1, R2 and capacitor CI.

Due to the charging/discharging time constant of C2, transistor Q1
The base of the transistor Q1 is designed so that four transistors Q1 are turned on only when the horizontal +lIl signal g is input. The horizontal synchronizing signal pulse (-IP) which is separated and output to the collector side of the transistor Q1 is input to the base of an impedance modulation transistor 102 connected to the connection point between the resistors R3 and R4.

This transistor 02 has its first transistor connected to the power supply terminal VCC, its emitter grounded via a resistor R;
It touches the base of 3 and is desecrated.

The base of the transistor Q3 is connected to the positive terminal of the bias voltage source 1 through a resistor R6 forming a differentiating circuit, and the horizontal synchronization pulse No. 111, which is a waveform obtained by differentiating the horizontal synchronization pulse No. 15 (1-(P), is connected to this base. Be impressed.

The emitter of the transistor Q3 is connected to the transistor Q3 via the resistor R7.
It is connected to the emitter of 4. This 1 ~ Ranjisk Q
4 has its emitter grounded via resistor R8, its collector connected to the power supply;: πVCC, and its base connected to the bias voltage source 1. For the transistor Q4 to which the voltage source E1 is applied, the differential signal is
When the value is 6 higher than E1, the 1-transistor Q3 is turned on.

Transistors Q5 and Q6 having similar configurations to the transistors Q3 and Q4 are provided so that the differential signal is supplied to the voltage source E.
When IJ=low, the 1-range disk Q5 is turned on.

Transistor Q5 has its emitter connected to the emitter of l-transistor Q6 via LR9, and its output connected to the collector of transistor Q3. Also, the ]rector (,1 current 1 of this transistor Q5)
- connected to the collector and base of transistor Q7 forming a mirror circuit and to the base of transistor Q8;

The emitter of the transistor Q6 is grounded through a resistor R10, the collector of the transistor Q6 is connected to the power supply terminal Vcc, and the base of the transistor Q6 is connected to the base of the transistor Q3.

The emitters of the transistors 07 and Q8 are connected to the power supply terminal VCC, respectively. This transistor Q8
The collector of is connected to the positive terminal of the reference voltage source E2 via the resistor +tii. Also, this 1 ~ Langista Q8''
The director is grounded via a capacitor C4, and
This is the output terminal of the waveform shaping detection circuit 18. Note that each negative electrode of the voltage source [:i and E2 is grounded.

The transistor 07 is turned on when either the transistor Q3 or Q5 is turned on, and the transistor Q8, which has the same base potential as the transistor Q1, is also turned on, and a current corresponding to the number of input differential signals is generated on the transistor side. Let it flow.

The capacitor C4 is charged by the current flowing to the collector side of the transistor Q8, and as its potential increases, the capacitor C4 is discharged through the resistor R11. The time constant of this capacitor +lC4 and resistor R11 is made to almost match the period of the normal horizontal sync signal pulsed IP, and when the normal horizontal synchronization I pulse HP is input, the voltage across the capacitor 04 is It is maintained at a constant value slightly higher than the voltage E2 (represented by this voltage IJE2) of the reference voltage source E2.

On the other hand, when the number of differential input signals increases, as in the case where the synchronous pulse waveform is disturbed by noise from a weak electric field tube, the transistor Q8 becomes
The period during which the current occurs increases and the voltage across capacitor 04 becomes sharper.

In other words, the noise state is detected based on the number of differential waves of the synchronously separated horizontal bright signal pulse 1''P for the input composite video signal, and a detected voltage corresponding to that number is output. There is.

By the way, the horizontal synchronizing signal pulse l-IP outputted to the collector side of the horizontal brightness separation circuit 12 is the phase detection circuit 1.
4 is input. This horizontal synchronization signal pulse I P is applied to the base of the transistor Q9 of the 11th node in J5 to the transistors Q9 and Q10 connected to the differential type.
A bias power supply [3 is applied to the base of the other transistor Q10.

Above 1- Ranjisk Q9. The emitter of Q10 is connected to H and grounded via a resistor R12. Further, the collector of the transistor Q10 is connected to the power supply terminal Vcc, and the collector of the transistor Q9 is connected to a pair of differential type transistors Q11. Each emitter of Q12 is connected.

These 1 to transistor Q11. A bias pressure source E4 is applied to the base of Q12 via resistors R, 13, and R14.

A sawtooth wave SAW from the sawtooth wave generation circuit 21 is applied to the base of the transistor Q11, and when the level is higher than the base potential of the transistor Q12 to be used, the transistor Qll is turned on.

The sawtooth wave generating circuit 21 is a flyback transformer 13.
A horizontal output pulse outputted from the side is integrated by a resistor R15 and a capacitor C5 to form a sawtooth wave, and this integrated wave output is applied to the base of a C transistor Q11 via a capacitor CG.

Both transistors Q11. Each collector of Q12 is
(Transistor Q forming a current mirror circuit)
13. Connected to the collector of Q14. These transistors Q13. The bases of Q14 are connected to each other, and each emitter is connected to the power supply terminal Vcc via resistors R16 and R17, respectively. The above transistor Q1
3 has its collector connected to the base. Thus, the output terminal of the transistor Q12 is used as the output terminal of the phase detection circuit 14, and the phase-compared comparison output is input to the filter circuit 15.

Incidentally, the emitter of the transistor Q9 is connected to the emitter of the phase detection current control transistor Q15. This transistor Q15 has its collector grounded via a resistor R17, and its base connected to a resistor R1.
8, the output voltage vO of the waveform shaping detection circuit 18 is applied.

The transistor Q15 forms a phase detection current control means in which the higher the voltage applied to its base, the smaller the current flowing between its emitter and collector, and the smaller the phase detection current becomes. That is, as the number of input differential signals increases, the output current of the phase detection circuit 14 is reduced, the amount of feedback applied to the horizontal oscillation circuit 16 via the filter circuit 15 is reduced, and the loop gain of the horizontal AFC circuit is reduced.

On the other hand, when the horizontal synchronizing signal pulse is separated without being disturbed by the nozzle under normal electric field strength, the detection voltage 0 becomes approximately E2, the transistor Q15 becomes sufficiently conductive, and the phase detection Increase the current. In other words, keep the loop gain as high as possible.

The input and output ends of the filter circuit 15 are grounded via a series circuit of a resistor R19 and a capacitor C7, and are also grounded via a lead C8.

The operation of one embodiment configured in this way will be explained below. l
I do it.

The composite video signal shown in FIG. 2(a) is input to the horizontal synchronization separation circuit 12! ;'jSCv, the transistor Q1 is turned on only when the horizontal synchronizing signal is inputted to and (input to the phase detection circuit 14).

This separated horizontal synchronizing signal pulse l-IF" is as shown in FIG. In this case, the waveform becomes as shown in FIG. 6(b).

Thus, the signal applied to the base of the transistor Q2 forming the differentiating circuit 17 is converted to a low impedance, outputted to its emitter side, and differentiated by the capacitor C3 and the resistor R6. When the water 1/synchronization signal pulsed IP is as shown in Fig. 2(b), this differential signal is as shown in Fig. 2(C).
In a weak electric field as shown in FIG. 2(d), the output waveform is as shown in FIG. 2(d).

The J differential signal shown in FIG. 2(C) or (d) is applied to the bases of transistors Q3 and R6, and the bias voltage E1 is applied to the bases of transistors Q4 and R5 paired with these transistors Q3 and R6. has been done. Therefore,
When the differential signal has a voltage of 11 or higher, transistor Q3
, R6 are turned on, and when the differential signal is less than voltage E1, transistors Q4 and R5 are turned on.

When either of the transistors Q3 or R5 turns on, a transistor Q7 forms a current mirror circuit;
Both R8 are turned on. When the transistor Q8 is turned on, the capacitor 04 is charged by the current flowing between its emitter and collector, and its output voltage 0 rises.

This output voltage VO is almost close to the base QL lightning voltage 2 as shown by the dashed line in Fig. 2(e) for the differential wave of the normal horizontal synchronizing signal pulse as shown in Fig. 2(C). level. On the other hand, as shown in FIG. 2(d), when the number of differential signals is large, the voltage level becomes high as shown by the broken line J in FIG. 2(C).

On the other hand, the horizontal synchronizing signal pulse HP and the sawtooth wave SAW
are input to the phase detection circuit 14, and detection signals having different output levels according to the phase difference between these two input signals are output to the filter circuit 15 side.

The horizontal oscillation circuit 1 then passes through this filter circuit 15.
The horizontal AFC control signal applied to the horizontal AFC control signal 6 controls the oscillation frequency of the horizontal oscillation circuit 16 to match the phase of the horizontal synchronizing signal pulse HP. In this case, the output voltage of the waveform layered detection circuit 18 is 0 to control the small emitter-collect current of the transistor Q15 to control the return frame suspension of the control signal for V AFC applied to the horizontal oscillation circuit 16. are doing.

That is, when the output voltage VO of the waveform shaping detection circuit 18 is small and the TV signal is at the normal electric field strength of 1.1, or when the TV signal is passed through the corner of the VTR and the TV signal is at the normal electric field strength: 1. 'I, the current flowing through the phase detection circuit 14 is large.

In other words, when the transistor Q9 is turned on, the current flowing between the collector and emitter is the sum of the component flowing through the resistor R12 and the current component flowing between the emitter and collector of the transistor Q15, and the detected current output from the phase detection circuit 14. It is made larger than in the case of weak electric field strength.

Therefore, by applying a sufficient phase detection voltage to the horizontal oscillation circuit 16 forming the horizontal AFC circuit, the horizontal deflection output can be locked to the horizontal synchronizing signal pulse separated from the input composite video signal. Furthermore, it is possible to deal with the case of a VTR reproduced signal.

In other words, even if the video signal is FM modulated by the expansion and contraction of the tape, the differential signal in this case has a waveform as shown in FIG.
O is low, and the detection current of the phase detection circuit 14 is large and horizontal
FC loop gain is kept large. Therefore, even if the position of the horizontal synchronization signal pulse IP changes, the phase of the horizontal oscillation circuit 16 is quickly controlled to match the phase of the horizontal synchronization pulse No. 15 HP, and horizontal lateral wobbling and bending can be reduced. .

On the other hand, when the output voltage of the waveform-shaping detection circuit 18 is large, the base potential of the transistor Q15 increases. increases, so the U current flowing between the emitter and collector of the transistor Q15 becomes smaller depending on the voltage.In other words, the detection current of the phase detection circuit 14 decreases, and the horizontal AFC loop gain is suppressed to a small value.Therefore, the noise This can prevent the oscillation frequency or phase of the horizontal oscillation circuit 16 from being disturbed (and causing jitter) more than necessary.

FIG. 3 shows a horizontal periodic signal reproducing circuit 31 according to another embodiment of the present invention.

This horizontal periodic signal regeneration circuit 31 includes the waveform shaping detection circuit 1
8 without inputting the output voltage VO to the phase detection circuit 14,
It is input to the filter circuit 32, and the filter characteristics are variably controlled by this output voltage VO.

This filter circuit 32 includes a field effect transistor (F
The source of ET)01G is connected to the input/output terminal, and the drain thereof is connected to the connection point between resistor R19 and T1 capacitor C7 via resistor R21.

Therefore, the output voltage V of the waveform shaping detection circuit 18.

(,1 is connected to the gate of FrETQIG via resistor R18, and the source and
Is the effective impedance between the drains iT? to change the filter characteristics.

That is, the higher the output voltage vO, the more the resistance R19 and -1[
The effective impedance caused by the distortion becomes small, and the loop gain of the horizontal AFC becomes small.

The configuration of other circuit parts is almost the same as that shown in FIG. In this case, the phase detection circuit 14 does not use the transistor Q15 in parallel with the resistor R12 shown in FIG. 1, but instead uses a parallel resistor consisting of resistors R12 and R17.

FIG. 4 shows the main part of yet another embodiment of the present invention.

In the case shown in Fig. 4, the detection period is changed by a horizontal AFC circuit to a pulse period (K
ey puts○ period), resistor R11 and reference voltage E2
This turns on the switch SW interposed between the

By turning on the switch SW during this pulse period, it is possible to increase the detection efficiency, and when the horizontal AFC circuit is not locked, the detection period is shortened and the charge m charged in the capacitor C4 is reduced. decreases, and the voltage of this capacitor J-C11 decreases, so that the horizontal phase detection current does not decrease and the horizontal AFC circuit can perform the pull-in operation, which is advantageous.

Note that the operation period of the waveform shaping detection circuit 18 is not limited to the one shown in FIG. good. For example, an analog switch or the like may be provided on the base side of the transistor Q8, and this switch may be turned on by a horizontal synchronizing pulse. In this case, it is sufficient that the power supply terminal VCC is applied to the base of the transistor Q8 when it is off.

1 and 3, the detection current of the phase detection circuit 14 and the filter characteristics of the filter circuit 32 may be variably controlled by the output voltage vO of the waveform shaping detection circuit 18.

In addition, the configuration of the waveform shaping detection circuit is such that it detects both the positive and negative polarities of the differential signal symmetrically in Figure 1, but it can be configured to detect only one polarity. Also good. It is also possible to detect the differential signal of the differential circuit 17 with a diode or the like, and provide the detected output with a time constant circuit using a resistor and capacitor. It is also possible to activate a multi-by-break or the like to output a voltage with a wider pulse width (a type of detection) when the number of differential inputs is large, and then average the output with a time constant circuit.

[Efficacy of invention! II! ] As described above, according to the present invention, the horizontal synchronizing signal separated from the input composite video signal is differentiated, the differentiated signal is detected, the nozzle level of the composite video signal is detected, and the nozzle level of the composite video signal is detected. J: Controls the loop gain or filter characteristics of the horizontal AFC circuit using voltage, so
It is possible to horizontally FC the circuit characteristics according to the state of the input video signal, suppressing horizontal jitter in weak electric field areas when receiving FV signals, and suppressing horizontal lateral vibration and bending during TVR playback. can be suppressed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is a waveform diagram illustrating the operation of one embodiment, and FIG. 3 is a block diagram showing another embodiment of the present invention. FIG. 4 is a circuit diagram showing the main parts of still another embodiment of the present invention, FIG. 5 is a block diagram showing a horizontal AFC circuit in a conventional example, and FIG. 6 is a normal electric field strength and a weak electric field strength. A waveform diagram showing the horizontal synchronizing signal separated at J3 in Figure 7 shows the electric field strength of jδ and V
FIG. 3 is a waveform diagram showing separated horizontal synchronization signals during 17R playback. 11...Horizontal friend number regeneration circuit 12...Horizontal synchronization, j, ifl path 14...Phase detection circuit 15...Filter circuit 1
6...Horizontal oscillation circuit C4...Capacitor Q15
...Control transistor R17...Resistor Fig. 4

Claims (4)

[Claims] (1) A horizontal synchronization separation circuit that separates a horizontal synchronization signal from an input composite video signal, a differentiation circuit that differentiates the separated horizontal synchronization signal, and a differential signal from this differentiation circuit that is detected and detected as a noise state. 1. A horizontal synchronization signal reproducing circuit comprising: a detection circuit that obtains a corresponding detection voltage; and a control circuit that controls the oscillation frequency of a horizontal oscillation circuit based on the detection voltage. (2) The first control circuit is connected in parallel to the resistor through which the detection current of the phase detection circuit forming the horizontal automatic frequency control circuit flows, and controls such that the larger the detection voltage, the smaller the current flowing through the collector-emitter and the series resistor. The horizontal synchronizing signal reproducing circuit according to claim 1, characterized in that the horizontal synchronizing signal reproducing circuit is formed by providing a transistor for the horizontal synchronizing signal. (3) The horizontal synchronizing signal reproducing circuit according to claim 1, wherein the first control circuit controls the filter characteristics of the filter circuit forming the horizontal automatic frequency control circuit using the detected voltage. . (4) The horizontal periodic signal reproducing circuit according to claim 1, wherein the first detection circuit has an operation period controlled by a pulse period obtained from the horizontal oscillation circuit.