JPS6313440A - Receiving device for spread spectrum signal - Google Patents

Abstract

PURPOSE:To attain the stable synchronizing holding in a spectrum communicating system with a good frequency using efficiency by detecting the maximum value of a matching filter output and using the time position to detect it as a transmitting signal system and a code word. CONSTITUTION:Only one period out of receiving signals composed of a continuous spread code is serially and parallelly converted, removed and held for one period. A matching film 5 with the held signal as an input changes hourly the coefficient so as to realize all patterns of a transmittable spread code, and counts the correlation concerning all assemblings of the receiving signal and the spread code. By detecting the time position in which the maximum value appears at the output of the matching filter 5, the transmitted information and the pattern of the diffusion code can be decided. A delaying locking loop 9, with the pattern of the decided spread code as a reference code, detects the correlation of the receiving signal to execute the one-code word period delaying and holds the period with the peak position.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a spread spectrum signal receiving device.

[Conventional technology]

The so-called spread spectrum method, in which an information signal is multiplied by a wideband spreading code and transmitted, and then despread and returned as a narrowband signal on the receiving side, is suitable for land transportation due to its excellent cross-band characteristics, fading resistance, and secrecy. Research and development is underway with the aim of applying it to telecommunications and satellite communications, but it has the drawback of being less efficient in frequency use than narrowband signaling systems. In contrast, in Japanese Patent Application No. 61033288, ``Spread Spectrum Communication System and Receiving Device J'', frequency utilization efficiency is improved based on the principle explained below. Spreading code (gold code)
Select one from among them and send it. On the receiving side, the correlation between this received signal and all spreading codes that may be transmitted is calculated, and data is determined based on the results. In this way, by transmitting multiple bits of information with one code word, utilization efficiency is improved.

[Problems to be Solved by the Invention] However, in general, wireless transmission paths are unstable systems, and it is difficult to maintain synchronization unless synchronous tracking is forced by some method.

An object of the present invention is to provide a spread spectrum receiving apparatus that maintains stable synchronization in a spectrum communication system that uses a plurality of spreading codes and has good frequency utilization efficiency.

[Means for solving problems]

The spread spectrum signal receiving device of the present invention includes a delay line for delaying a received signal consisting of continuous spread codes by one code word period, and a delay line for extracting one code word in parallel from the received signal on the delay line for one code word period. a serial-to-parallel conversion circuit for holding the received signal in the serial-to-parallel conversion circuit; a matched filter for sequentially calculating correlations by changing coefficients over time for the received signal held in the serial-to-parallel conversion circuit to realize all transmission patterns of a code word; a maximum value detection circuit that detects the maximum value of the output of the filter; a conversion circuit that converts the time position at which the maximum value detection circuit determines that the maximum value is detected into a transmission signal sequence and a transmission button of a code word; and the delay A register that holds the line output for one code, and a delay that detects the correlation between the signal held in the register and the transmission button of the conversion circuit output and supplies a timing signal to the serial-parallel conversion circuit and the register. It consists of a lock loop.

[Effect]

In the spread spectrum signal receiving device of the present invention,
Out of the received signal consisting of continuous spreading codes, only one period is converted into serial/parallel and extracted and held for one period. A matched filter that receives this retained signal as input changes its coefficients over time to realize all the patterns of spreading codes that can be transmitted, and correlates the received signal with all combinations of spreading codes. Calculate. Since the cross-correlation of the spreading codes is sufficiently small and almost orthogonal, the maximum value appears in the output when the received signal and the spreading code of the coefficients of the matched filter match. Therefore, by detecting the time position at which the maximum value appears in the output of the matched filter, the transmitted information and the spread code can be determined. The delay lock loop uses the determined spread code pattern as a reference code, detects the correlation with the received signal delayed by one code word period, and maintains the period based on the peak position.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings. FIG. 1 is a diagram showing an embodiment of a spread spectrum signal receiving apparatus of the present invention. A signal consisting of consecutive spreading codes received by antenna 1 is synchronously detected by synchronous detector 2 and then input to delay line 3 having a delay time of one code word period. The serial-to-parallel conversion circuit 4 extracts one period of the spreading code from the received signal on the delay line 3 by performing serial-to-parallel conversion and holds it for one period. For the received signal held in the serial-to-parallel conversion circuit 4, the matched filter 5 changes its coefficients over time so as to realize all the transmission patterns of the spreading code, and calculates the correlation between the received signal and the spreading code. do. Since the cross-correlation between different spreading codes is sufficiently small and can be considered to be nearly orthogonal, the maximum value appears in the output when the coefficients of the matched filter match the received signal. In other words, the time at which the output of the matched filter reaches its maximum value is uniquely determined by the transmission button. Therefore, this peak is detected by the maximum value detection circuit 6, and the time position at that time is converted into an information signal by the conversion circuit 7. At the same time, the conversion circuit 7 outputs the received signal bang determined from the time position to the delay lock loop 9. Register 8 holds the output of delay line 3 for one symbol. The delay lock loop 9 detects the correlation peak position between the signal held in the register 8 and the bang output of the conversion circuit 7, maintains synchronization, and outputs an appropriate timing signal to the serial/parallel conversion circuit 4 and the register 8.

Next, a more specific embodiment of the receiving apparatus in the embodiment shown in FIG. 1 will be described. This embodiment uses a gold code with a length of 7 chips as the spreading code.

FIG. 2 shows a more specific embodiment of the receiving device shown in FIG. A signal received at an input terminal 301 is demodulated into a baseband signal by a synchronous detector 2, and then input to a delay line 3 having a delay time of one code word period. A serial-to-parallel converter circuit 4, which is connected to each tap of the delay line 3 and consists of seven parallel stages of A/D (analog-digital) converters, converts one period of the spreading code from the received signal on the delay line 3 into serial and parallel formats. Convert it, take it out, and hold it for one cycle. Since the serial-to-parallel conversion circuit 4 is driven by a tarlock circuit 10 synchronized with the spread code, the voltage corresponding to each chip of the Gold code is sampled and held. A matched filter 5
calculates the correlation by sequentially changing the coefficients to eight types of gold codes that may be transmitted. The matched filter 5 includes multipliers 50 to 56, a counter 57, and a ROM (ROM) that stores Gold code patterns that may be transmitted.
(Read Only Memory) 58 and five addition/synthesis circuits. The counter 57 is reset by the output of the clock circuit 10 when one period of the gold code is sent to the serial/parallel conversion circuit 4, and the counter 57 generates a clock 200 having an oscillation frequency 8/7 times that of the clock 202. Count and input the value as the address of the ROM 58. The ROM 58 reads out the gold code pattern stored in the memory corresponding to the input address using the clock 200 as a read pulse.

Multiplier 5 multiplier 5
The correlation is calculated by multiplying the received signal by 0 to 56 and then adding the results in a synthesis and addition circuit 59. Since the cross-correlation between the eight types of gold codes that may be transmitted is sufficiently small and these codes can be considered orthogonal to each other, the addition and synthesis circuit 5
The two outputs are the received signal and the coefficients of the matched filter 5, RO
The maximum value is reached when the output of M58 matches. Therefore, the transmitted sequence can be decoded by determining the time position at which this maximum value appears.

The process is shown below. First, the maximum value detection circuit 6 detects the time when the output of the matched filter 5 takes the maximum value. The maximum value is stored in the memory 60, and the signal input to the maximum value detection circuit 6 is compared with the memory contents in the comparator 61. Write pulse to memory 60
and sends it to memory 70. In the memory 60, this comparator 6
When a write pulse from 1 comes, the input signal at that time is written as a new value. During this process, the maximum value is stored in the memory 60. This process is driven by a clock 200. The contents of the memory 60 are stored in the clock circuit 1.
The signal from 0 is reset every time a new correlation characteristic between the received signal and the Gold code is input to the maximum value detection circuit 6. The signal from the comparator 61 is also supplied to the memory 70. The memory 70 stores the contents of the counter 72, which is reset by the output of the clock circuit 10, based on the signal from the comparator 61, thereby storing the time when the input signal takes the maximum value. The contents of memory 70 are also reset with a signal from clock circuit 10. The contents of the memory 70 are converted into transmission data and transmission patterns by the ROM 71, and the signals from the clock circuit 10 are read out and output as pulses. Transmission data is subjected to parallel-to-serial conversion by a conversion circuit 73 driven by a clock 201 that matches the information rate, and is output from a terminal 11. On the other hand, the transmission pattern is input to the delay lock loop 9. Using the transmission pattern determined in this way as a reference code, synchronization can be maintained by detecting the correlation peak position with the received signal delayed by one period.

The process will be explained below. The output of the delay line 3 is first integrated in one chip by an integration-discharge filter 80 driven by a clock circuit 10 in a register 8.
The data is digitized by a D converter 81 and then sequentially input to a shift register 82. The delay lock loop is
Gold code for one period held in this way and ROM7
A correlation is calculated by multiplying the transmission pattern of the output of 1 by multipliers A1 to A7 and multipliers B1 to B7, respectively, and adding the results in synthesis and addition circuits 91 and 92, and the difference is calculated by subtracter 93. Find it by In this case, if the transmission patterns supplied to the multipliers 81 to B7 are shifted one chip cycle with respect to the transmission patterns supplied to the multipliers A1 to A7, the subtracter 93 is shifted in accordance with the timing of the clock 202. The output changes. This situation is shown in FIG. The output of this subtracter 93 is D/
A (digital-to-analog) converter 94 converts the signal to
ge Controlled 0scillator)
control. Using the output of this VCO95 as a reference signal,
Clock 202 of clock circuit 10 drives A/D converter 80. In addition, the counter 101 has a clock 202.
A pulse is sent to the D/A converter 94 every time 7 counts. When the circuit is configured in this way, feedback is applied to delay the timing of the clock 202 when it is early, and to accelerate it when the timing is slow, so that the timing of the clock 202 is always the same as the maximum and minimum of the output of the subtracter 93. Captured at midpoint. Since the timing of the clock 202 captured in this way is ahead of the actual timing by 1/2 chip time, the delay circuit 102
The signal is delayed by 1/2 chip time and corrected to the correct timing, and then supplied to the serial/parallel conversion circuit 4, matched filter 5, maximum value detection circuit 6, and conversion circuit 7.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a spread spectrum signal receiving apparatus that maintains stable synchronization.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the receiving device of the present invention, FIG. 2 is a block diagram showing details of the receiving device of FIG. 1,
FIG. 3 is an explanatory diagram showing the operation of FIG. 2. 3... Delay line, 4... Serial/parallel conversion circuit, 5... Matched filter, 6... Maximum value detection circuit, 7... Conversion circuit, 8... Register, 9... Delay lock loop. Figure 1

Claims (1)

[Claims] a delay line that delays a received signal consisting of continuous spreading codes by one code word period; a serial-to-parallel conversion circuit that extracts one code word in parallel from the received signal on the delay line and holds it for one code word period; A matched filter that sequentially calculates correlations by changing coefficients over time of the received signal held in the parallel conversion circuit to realize all transmission patterns of the code word, and a maximum value that detects the maximum value of the output of the matched filter. a detection circuit, a conversion circuit that converts the time position at which the maximum value detection circuit determines that the maximum value has been detected into a transmission signal sequence and a transmission pattern of a code word, and a register that holds the delay line output for one code. , comprising a delay lock loop that detects the correlation between the signal held in the register and the transmission pattern of the output of the conversion circuit and supplies a timing signal to the serial/parallel conversion circuit and the register. A receiver for spread spectrum signals.