JPS63133571A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To achieve the formation of a graft base region having a submicron width by a method wherein, when a polycrystalline semiconductor layer is wet-etched by making use of a side wall as a mask, in undercut part is formed at the polycrystalline semiconductor layer located under the side wall. CONSTITUTION:After a polycrystalline Si layer 7 undoped with an impurity has been formed on the whole surface by a CVD method, an SiO2 layer doped with boron is formed on the surface of this layer by a CVD method. After that, by etching the whole surface by an RIE method, a side wall 9 of SiO2, acting as an etching mask layer, is formed on the side wall of recessed part 8 at the Si layer 7 formed by an opening 6. Then, the Si layer 7 is etched by KOH by making use of side wall 9 as a mask. The etching process is stopped on the substrate 1 due to the selectively of the KOH. In order to keep a distance from a P<+> type graft base region 13 and an N<+> type emitter region 15 which are to be formed later, an undercut part 10 is formed by overetching the Si layer 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of forming a contact region between a wiring layer for leading out an external electrode and an operating region in a semiconductor device, particularly.

[Summary of the invention]

The present invention is a method for manufacturing a semiconductor device, in which a sidewall doped with impurities is formed on the sidewall of an opening provided in a multilayer film on an emitter and base region through a polySt layer,
By diffusing impurities from this sidewall into the substrate, a contact region with the base region is formed, and by using this sidewall to form an insulating layer, it is possible to reliably separate the emitter and base. This is what I did.

[Conventional technology]

For example, as shown in Figure 3, a bipolar transistor (2
In 1), there is a structure in which a polycrystalline Si layer (4) doped with boron B is used as a wiring layer for leading out external electrodes from the base region (11). In the figure, (1) is an St substrate, (2) is a LOGO3 oxide film, and (3) is a 5i0
2jii, (13) is a graft base region, (15) is an emitter region, and (19) is a collector region.

[Problem that the invention seeks to solve]

When manufacturing a bipolar transistor (21) having a structure in which the above-mentioned polycrystalline Si layer (4) is used as a wiring layer for taking out external electrodes, polycrystalline Si Fit (4)
An allowance for mask alignment is required between the O5 oxide film (2) and the width W of the graft base region (13), which is the contact region with the polycrystalline Si layer (4) of the base region (11), to be made small. There are limits to Therefore, the proportion occupied by the graft base region (13) is larger than that of the base region (11) that is directly involved in the operation, so the existence of this region (13) causes the bipolar transistor (21
) has become an obstacle to speeding up and miniaturization.

The present invention provides a method for manufacturing a semiconductor device that can solve the above problems.

[Means for solving problems]

In the present invention, a multilayer III! consisting of at least a wiring layer (4) and an insulating layer (3) formed on the wiring layer (4) on the semiconductor substrate (1). (5) and the process of forming this multilayer film (
5) forming an opening (6) to the substrate (1);
A polycrystalline semiconductor layer (7) covers the entire surface including this opening (6).
and a step of forming, by anisotropic etching, a sidewall (9) which will serve as a notching mask layer on the sidewall of the recess (8) of the polycrystalline semiconductor layer (7) formed by this opening (6). and a step of etching the polycrystalline semiconductor N (7) using this sidewall (9), and anisotropically etching the polycrystalline semiconductor layer (7) formed on the sidewall of the opening (6) and the sidewall (9). A step of forming an insulating layer (12) by etching, and a step of introducing impurities into the semiconductor substrate (1) from the sidewall (9) or wiring layer (4) via the polycrystalline semiconductor layer (7) to form a graft base region. (
13).

In the above step, the sidewall (9) or wiring layer (4) for introducing impurities into the semiconductor substrate (1) is doped with a required impurity;
When wet-etching the polycrystalline semiconductor layer (7) using 9) as a mask, an undercut portion (lO) is created in the polycrystalline semiconductor layer (7) under the sidewall (9).

[Effect]

For finely forming the graft base region (13),
Sidewall (9) or wiring layer (4) containing impurities
Diffusion into the semiconductor substrate (1) from the polycrystalline semiconductor N(
This is made possible by forming an undercut (10) under the sidewall (9) with good controllability when etching 7). Further, by forming the undercaft portion (10) by wet etching using the sidewall (9) as a mask, it can be formed without mask alignment. Furthermore, the separation of emmi 7ta and bass,
The insulating layer (1) is placed on the sidewall (9) containing the impurity.
2) can be achieved by forming a new sidewall that covers the above.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the present invention is applied to a contact to a base region of an NPN I-transistor will be described with reference to the drawings.

First, as shown in FIG. 1A, after forming an oxidized 1!i! (21) on a <111> N-type St substrate (11) by the LOCOS method, a 5tCh layer (3),
A polycrystalline (poly) St layer (4) and a 5i (h layer (3) doped with boron B at a high concentration, which will serve as a wiring layer for taking out external electrodes)
) are stacked to form a multilayer film (5). Thereafter, openings (6) are formed in predetermined portions of the multilayer film (5) (portions corresponding to the emitter and base) by RIE (reactive ion etching). When forming this opening (6), the lowermost SiO2 layer (3) is formed by low-damage RIE, or by RIE halfway and then solution etching to prevent damage to the substrate (1). Reduce.

Next, as shown in FIG. 1B, a polycrystalline (poly) St layer (7) to which no impurities have been added is deposited by CVD on the entire surface.
After that, a 5i02 layer doped with boron B, which is the same P-type impurity as the base region (11), is formed by CVD.
Form with D. After this, the entire surface is etched by RIE, and the pure poly S formed by the opening (6) is etched.
A sidewall (9) of 5i02, which will serve as an etching mask layer, is formed on the sidewall of the recess (8) of the i-layer (7).

Next, as shown in FIG. 1C, the pure poly-Si layer (7) is etched with KOH using the sidewall (9) as an etching mask. During this etching,
Due to the selectivity of KOJI, etching stops on the <111> substrate (1), but in order to maintain a distance between the P medium-sized graft base region (13) to be formed later and the N+ type emitter region (Step 5), Overetch the pure poly StJ'ii (7) to create an undercut (10).

Next, as shown in the first diagram, a P-type impurity is introduced into the St substrate (1) by ion implantation or the like to form a base region (11), and then an insulating layer such as a SiN layer (12) or a 5i02 layer is formed. It is formed on the entire surface and then annealed.

During this annealing, the substrate (
By diffusing B to 11, the graft base region @(
13). In addition, as in this example, 5t02J
If the poly Si (514) which is the wiring layer on W (3) is doped with B at a high concentration, B will be added to the sidewall (9).
This poly S i Jii (4
) into the substrate (1) to form the graft base region (13). In addition, the entire surface is SiN
When forming M (12), the undercasing part (10)
It is preferable to carry out low pressure CVD so that SiN can be well penetrated into the inside.

Next, as shown in FIG. 1E, SiN 5 (12
), and by further covering the sidewall (9) with SiN Jii (12) to form a new sidewall, separation between the emitter and base can be ensured.

Next, as shown in FIG. 1F, an emitter region (15) is formed, for example, by forming and diffusing a poly-Si layer (14) heavily doped with N-type impurities over the entire surface.

Finally, as shown in FIG. 1G, an emitter electrode (16), a base electrode (17), and a collector electrode (not shown) are formed by a normal process to obtain a bipolar transistor (18) of the present invention. (19) becomes the collector area.

Next, an example will be described in which an undercut portion (lO) is formed with good controllability in order to suppress variations in cJε and Vε80.

As shown in FIG. 2A, the same process as in the above embodiment is performed until the side wall (8) is formed on the side wall of the recess (8) of the pure poly-Si layer ('/).

Next, as shown in FIG. 2B, impurities are introduced into the exposed portion of the poly-Si layer (7) by ion-implanting N2.02 or the like into the entire surface using the sidewall (9) as a mask. After this, no annealing is performed.

Next, as shown in FIG. 2C, etching is performed using hot phosphoric acid or the like to selectively remove the portions of the poly-Si layer (7) into which impurities have been implanted.

Next, as shown in the second diagram, etching is performed using KOH to form an undercast part (10) on the pure poly Si Jii (71).After this, the process is the same as the process from the first diagram in the above example. A bipolar transistor (see FIG. 1G) is manufactured by using this method.This manufacturing method increases the reproducibility of forming the undercut portion (10), thereby increasing the reliability of separation between the emitter and the base.

〔Effect of the invention〕

According to the present invention, a polycrystalline semiconductor layer is etched using an insulating sidewall doped with impurities as a mask,
By leaving a submicron-wide polycrystalline semiconductor layer on the sidewall of the opening formed in the polyN film, and diffusing impurities from this sidewall into the polycrystalline semiconductor layer and the semiconductor substrate,
A graft base region that becomes a contact region with a wiring layer for taking out an external electrode can be formed with a submicron width and without mask alignment. In addition, by forming a new sidewall by forming an insulating layer on the sidewall with impurities left in place, it is possible to reliably separate the emitter and base to prevent short-circuiting.

[Brief explanation of the drawing]

FIG. 1 is a process diagram of an embodiment, FIG. 2 is a process diagram of another embodiment, and FIG. 3 is a sectional view of a conventional example. ill is an St substrate, (4) is a doped polySi layer, (5
) is a multilayer film, (6) is an opening, (7) is a Piervory St.
layer, (8) is the recess, (9) is the sidewall, (10)
(12) is a SiN layer, (13) is a graft base region, and (18) is a bipolar transistor.

Claims (1)

[Claims] A step of forming a multilayer film including at least a wiring layer and an insulating layer formed thereon on a semiconductor substrate; a step of forming an opening to the substrate in the multilayer film; and a step of forming an opening to the substrate in the multilayer film. a step of forming a polycrystalline semiconductor layer on the entire surface including the inside of the polycrystalline semiconductor layer; a step of forming an etching mask layer by anisotropic etching on the sidewall of the recess of the polycrystalline semiconductor layer formed by the opening; etching the polycrystalline semiconductor layer; forming an insulating layer by anisotropic etching on the polycrystalline semiconductor layer formed on the sidewall of the opening and the etching mask layer; and etching the polycrystalline semiconductor layer on the semiconductor substrate. A method for manufacturing a semiconductor device including a step of introducing impurities through a crystalline semiconductor layer.