JPS63133562A - Manufacture of groove type capacitor - Google Patents
Manufacture of groove type capacitorInfo
- Publication number
- JPS63133562A JPS63133562A JP28021586A JP28021586A JPS63133562A JP S63133562 A JPS63133562 A JP S63133562A JP 28021586 A JP28021586 A JP 28021586A JP 28021586 A JP28021586 A JP 28021586A JP S63133562 A JPS63133562 A JP S63133562A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- film
- trench
- implanted
- silanol
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000005468 ion implantation Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000012535 impurity Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 12
- SCPYDCQAZCOKTP-UHFFFAOYSA-N silanol Chemical compound [SiH3]O SCPYDCQAZCOKTP-UHFFFAOYSA-N 0.000 claims abstract description 11
- 238000010884 ion-beam technique Methods 0.000 claims description 7
- 239000007943 implant Substances 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 238000010030 laminating Methods 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 150000002500 ions Chemical class 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- 229910052785 arsenic Inorganic materials 0.000 abstract description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 description 8
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- -1 arsenic ions Chemical class 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 150000004819 silanols Chemical class 0.000 description 1
- 229910021642 ultra pure water Inorganic materials 0.000 description 1
- 239000012498 ultrapure water Substances 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体基板に溝を堀り、溝の内壁に均一に不
純物を注入する溝形キャパシタの製造方法に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a trench capacitor, which involves digging a trench in a semiconductor substrate and uniformly implanting impurities into the inner wall of the trench.
従来の技術
従来の溝形キャパシタの製造方法゛では、溝の内壁に沿
って拡散領域を形成するにあたりイオン注入法が多用さ
れている。2. Description of the Related Art In conventional methods of manufacturing trench capacitors, ion implantation is often used to form diffusion regions along the inner walls of trenches.
この溝形キャパシタの製造方法は、溝を形成した後、溝
の内壁に不純物を注入するためにイオンビームを基板面
に対して垂直方向から5〜9度程度傾けてイオン注入を
行い、熱処理を施こして溝の側壁部と底部に拡散領域を
形成し、この後、溝の内壁にキャパシタ用の誘電体膜と
キャパシタの一方の電極となる導電膜を順次形成するも
のである。なお、イオン注入時の基板面に対して垂直方
向からのイオンビームの傾きをチルト角度と記す。The method for manufacturing this trench capacitor is to form a trench, then perform ion implantation by tilting the ion beam at an angle of about 5 to 9 degrees from the perpendicular direction to the substrate surface in order to implant impurities into the inner wall of the trench, followed by heat treatment. A diffusion region is formed on the sidewalls and bottom of the trench, and then a dielectric film for a capacitor and a conductive film to be one electrode of the capacitor are sequentially formed on the inner wall of the trench. Note that the inclination of the ion beam from the direction perpendicular to the substrate surface during ion implantation is referred to as a tilt angle.
発明が解決しようとする問題点
このように従来の製造方法では、イオン注入時に、チル
ト角度を設けた場合、不純物が溝の側壁部に注入される
ものの溝の底部にはより多く不純物が注入されるため、
溝の底部の不純物濃度が非常に高(なる。この結果、溝
内部にキャパシタ用の酸化膜を形成するとき、この酸化
膜の膜厚に不均一性が生じること、また、溝の底部では
イオン注入による損傷が大きいためこの部分の酸化膜の
膜質が悪くリーク電流の増加をともなうことにより、容
量特性に不安定性が生じる。Problems to be Solved by the Invention As described above, in the conventional manufacturing method, when a tilt angle is set during ion implantation, impurities are implanted into the side walls of the trench, but more impurities are implanted into the bottom of the trench. In order to
The impurity concentration at the bottom of the trench is extremely high.As a result, when an oxide film for a capacitor is formed inside the trench, the thickness of this oxide film becomes non-uniform, and ions are generated at the bottom of the trench. Since the damage caused by the implantation is large, the quality of the oxide film in this area is poor, and leakage current increases, causing instability in the capacitance characteristics.
問題点を解決するための手段
これらの問題点を解決するために溝の側壁部と底部への
不純物のイオン注入を各別に行う。このために、第1回
目の側壁へのイオン注入の前に、溝の底部にイオンビー
ムを遮蔽する膜を被着させ、この膜をマスクとして5〜
100度のチルト角度を設けて溝の側壁部にイオン注入
を行う。次に、溝の底部に被着した膜を除去した後、溝
の底部にイオン注入を行う。Means for Solving the Problems In order to solve these problems, impurity ions are implanted into the sidewalls and bottom of the trench separately. For this purpose, before the first ion implantation into the sidewalls, a film that shields the ion beam is deposited on the bottom of the groove, and this film is used as a mask for the 5-
Ions are implanted into the sidewalls of the trench with a tilt angle of 100 degrees. Next, after removing the film deposited on the bottom of the trench, ions are implanted into the bottom of the trench.
作用
溝の底部にシラノールの被膜を付け、この膜を底部への
イオン注入のマスクとすることにより、溝の側壁部と底
部へのイオン注入を別々に行うことができ、溝の内壁に
均一な不純物濃度の拡散領域が形成できる。By applying a silanol film to the bottom of the working groove and using this film as a mask for ion implantation into the bottom, ion implantation into the sidewalls and bottom of the groove can be performed separately, resulting in a uniform coating on the inner wall of the groove. A diffusion region with impurity concentration can be formed.
実施例
本発明の溝形キャパシタの製造方法の実施例を第1図に
示した工程断面図を参照して説明する。Embodiment An embodiment of the method for manufacturing a trench capacitor according to the present invention will be described with reference to the process cross-sectional diagram shown in FIG.
まず、シリコン基板1の上に酸化シリコン膜2を形成し
、写真食刻法により酸化シリコン膜2に1μ涌×1μ餉
の開口を設け、この開口よりドライエツチングを施こし
、シリコン基板1の中に深さ4μ曙の溝3を形成する(
第1図a)。First, a silicon oxide film 2 is formed on a silicon substrate 1, and an opening of 1 μm x 1 μm is formed in the silicon oxide film 2 by photolithography. Dry etching is performed through this opening to form an inside of the silicon substrate 1. Form groove 3 with a depth of 4μ in (
Figure 1 a).
7000r、p、−以上でシリコン基板1を回転させな
がら、シラノールの溶液を滴下してシラノール被膜4を
形成する。このとき、溶液が溝底部に塗布され、溝側壁
部にはほとんど塗布されない(第1図b)。While rotating the silicon substrate 1 at a speed of 7000 r, p, - or more, a silanol solution is dropped to form a silanol film 4. At this time, the solution is applied to the bottom of the groove, and is hardly applied to the side walls of the groove (FIG. 1b).
この、シラノール被膜を溝底部のマスクとして、チルト
角度を5〜9度もたせて200KeVの高加速電圧で砒
素イオン(As”)5の注入を行う(第1図C)。この
とき、溝の側壁にはイオン注入層6が形成されるが、底
部にはイオン注入層が形成されない。Using this silanol film as a mask at the bottom of the groove, arsenic ions (As'') 5 are implanted at a high acceleration voltage of 200 KeV with a tilt angle of 5 to 9 degrees (Fig. 1C). An ion implantation layer 6 is formed at the bottom, but no ion implantation layer is formed at the bottom.
この後、弗酸を超純水で希釈した液でシラノールの被膜
4を除去し、20KeV程度の低加速電圧で再び砒素イ
オン(As”)7の注入を行う(第1図d)。2回目の
イオン注入では溝の底部にのみイオン注入層8が形成さ
れ側壁部にはほとんど注入されない。After that, the silanol film 4 is removed with a solution prepared by diluting hydrofluoric acid with ultrapure water, and arsenic ions (As") 7 are implanted again at a low acceleration voltage of about 20 KeV (Fig. 1d). Second time In the ion implantation, the ion implantation layer 8 is formed only at the bottom of the groove, and is hardly implanted into the sidewalls.
この後、熱処理を施し、溝の内壁に不純物濃度が均一で
拡散長の浅い拡散領域9を形成する。Thereafter, a heat treatment is performed to form a diffusion region 9 having a uniform impurity concentration and a shallow diffusion length on the inner wall of the groove.
(第1図e)。(Figure 1e).
次に、シリコン基板1の表面および溝3の内壁に100
〜500A程度の厚さの酸化シリコン膜10を成長させ
てキャパシタ用の誘電体膜を形成させた後、この上にキ
ャパシタの一方の電極となるポリシリコン膜11を30
00A形成することにより、溝形キャパシタが完成する
(第1図f)。Next, 100 ml was applied to the surface of the silicon substrate 1 and the inner wall of the groove 3.
After growing a silicon oxide film 10 with a thickness of about 500 Å to form a dielectric film for a capacitor, a polysilicon film 11 that will become one electrode of the capacitor is grown on top of the silicon oxide film 10 with a thickness of about 300 Å.
By forming 00A, a trench capacitor is completed (FIG. 1f).
なお、キャパシタの他方の電極は拡散領域9である。ま
た、イオンビームを遮蔽する膜として実施例ではシラノ
ールの被膜を使用したが、レジスト膜であってもよい。Note that the other electrode of the capacitor is the diffusion region 9. Furthermore, although a silanol film was used in the embodiment as a film for shielding the ion beam, a resist film may also be used.
発明の効果
以上のように本発明によれば、溝の内禮全体に不純物濃
度が均一な拡散領域が得られるため、キャパシタ用の酸
化膜が均一な膜厚で、かつ、良質な膜となり、容量特性
が安定した溝形キャパシタが得られる。Effects of the Invention As described above, according to the present invention, a diffusion region with a uniform impurity concentration can be obtained throughout the inner groove, so that an oxide film for a capacitor can have a uniform thickness and a good quality. A trench capacitor with stable capacitance characteristics can be obtained.
第1図は本発明の溝形キャパシタの製造方法による実施
例を示す工程断面図である。
1・・・・・・シリコン基板、2,10・・・・・・酸
化シリコン膜、3・・・・・・溝、4・・・・・・シラ
ノール被膜、5,7・・・・・・砒素イオン(As”)
、6.8・・・・・・イオン注入層、9・・・・・・
拡散領域、11・・・・・・ポリシリコン膜。
代理人の氏名 弁理士 中尾敏男 ほか1名4゛°−シ
ラノールっ邊友用(
第1図
9− 紘詐幡を収FIG. 1 is a process sectional view showing an embodiment of the method for manufacturing a trench capacitor according to the present invention. 1... Silicon substrate, 2, 10... Silicon oxide film, 3... Groove, 4... Silanol coating, 5, 7...・Arsenic ion (As”)
, 6.8... ion implantation layer, 9...
Diffusion region, 11... Polysilicon film. Name of agent: Patent attorney Toshio Nakao and one other person
Claims (3)
イオンビームを遮蔽する膜を被着する工程と、同膜をマ
スクとしてチルト角度をもたせてイオン注入法により不
純物を前記溝の側壁部に注入する工程と、前記膜を除去
した後に、再度イオン注入法により前記溝の底部に不純
物を注入する工程と、前記溝の内壁にキャパシタ用の誘
電体膜と、キャパシタの一方の電極となる導電膜を順次
積層する工程とを備えたことを特徴とする溝形キャパシ
タの製造方法。(1) A process of forming a groove in a semiconductor substrate, a process of depositing a film to shield the ion beam on the bottom of the groove, and an ion implantation method using the film as a mask at a tilt angle to implant impurities into the groove. a step of implanting an impurity into the side wall portion, a step of implanting an impurity into the bottom of the trench again by ion implantation after removing the film, a dielectric film for a capacitor on the inner wall of the trench, and one electrode of the capacitor. 1. A method for manufacturing a trench capacitor, comprising the step of sequentially laminating conductive films.
あることを特徴とする特許請求の範囲第1項に記載の溝
形キャパシタの製造方法。(2) The method for manufacturing a trench capacitor according to claim 1, wherein the film that shields the ion beam is a silanol film.
あることを特徴とする特許請求の範囲第1項に記載の溝
形キャパシタの製造方法。(3) The method for manufacturing a trench capacitor according to claim 1, wherein the film that shields the ion beam is a photoresist film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28021586A JPS63133562A (en) | 1986-11-25 | 1986-11-25 | Manufacture of groove type capacitor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP28021586A JPS63133562A (en) | 1986-11-25 | 1986-11-25 | Manufacture of groove type capacitor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63133562A true JPS63133562A (en) | 1988-06-06 |
Family
ID=17621914
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP28021586A Pending JPS63133562A (en) | 1986-11-25 | 1986-11-25 | Manufacture of groove type capacitor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63133562A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5177030A (en) * | 1991-07-03 | 1993-01-05 | Micron Technology, Inc. | Method of making self-aligned vertical intrinsic resistance |
US5699292A (en) * | 1996-01-04 | 1997-12-16 | Micron Technology, Inc. | SRAM cell employing substantially vertically elongated pull-up resistors |
US5751630A (en) * | 1996-08-29 | 1998-05-12 | Micron Technology, Inc. | SRAM cell employing substantially vertically elongated pull-up resistors |
US5808941A (en) * | 1996-01-04 | 1998-09-15 | Micron Technology, Inc. | SRAM cell employing substantially vertically elongated pull-up resistors |
-
1986
- 1986-11-25 JP JP28021586A patent/JPS63133562A/en active Pending
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5177030A (en) * | 1991-07-03 | 1993-01-05 | Micron Technology, Inc. | Method of making self-aligned vertical intrinsic resistance |
US5699292A (en) * | 1996-01-04 | 1997-12-16 | Micron Technology, Inc. | SRAM cell employing substantially vertically elongated pull-up resistors |
US5732023A (en) * | 1996-01-04 | 1998-03-24 | Micron Technology, Inc. | SRAM cell employing substantially vertically elongated pull-up resistors |
US5808941A (en) * | 1996-01-04 | 1998-09-15 | Micron Technology, Inc. | SRAM cell employing substantially vertically elongated pull-up resistors |
US5844838A (en) * | 1996-01-04 | 1998-12-01 | Micron Technology, Inc. | SRAM cell employing substantially vertically elongated pull-up resistors |
US5943269A (en) * | 1996-01-04 | 1999-08-24 | Micron Technology, Inc. | SRAM cell employing substantially vertically elongated pull-up resistors |
US5969994A (en) * | 1996-01-04 | 1999-10-19 | Micron Technology, Inc. | Sram cell employing substantially vertically elongated pull-up resistors |
US5995411A (en) * | 1996-01-04 | 1999-11-30 | Micron Technology, Inc. | SRAM cell employing substantially vertically elongated pull-up resistors |
US5751630A (en) * | 1996-08-29 | 1998-05-12 | Micron Technology, Inc. | SRAM cell employing substantially vertically elongated pull-up resistors |
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