JPS63132575A - Circuit for detecting variable point of binary data - Google Patents

Abstract

PURPOSE:To speed up a detecting operation by providing a serial/parallel converting circuit, first-n-th latching circuits for inputting simultaneously the data of one unit being its output at every bit, the (n+1)-th latching circuit to which the output of the n-th latching circuit is inputted, and an EXOR circuit for setting the outputs of these adjacent latching circuits, as two inputs, respectively. CONSTITUTION:A serials/parallel converting circuit 2 inputs a serial binary data and outputs simultaneously a data consisting of (n) bits of one unit at every prescribed timing. To latching circuits (D flip flop) A1-An, the output of the converting circuit 2 is inputted, and to a circuit An+1, the output of the circuit An is inputted. Also, EXOR circuits C1-Cn set the outputs of each adjacent circuit of the circuits A1-An as two inputs, respectively, and a BXOR circuit Cn+1 sets each outputs of the (n+1)-th and the first latching circuit An+1, A1, as two inputs. According to such a constitution, with regard to a data of one unit, and also, with regard to the final bit of the data immediately before and the first data of the data concerned, whether a variation point exists or not can be detected immediately. By detecting the existence of this variation point, and counting the number of data until the variation point is generated, the code data of an MU system based on the result of its counting can be selected.

Description

DETAILED DESCRIPTION OF THE INVENTION (It) Field of Industrial Application The present invention relates to binary data that can be used in facsimile machines, image scanners (image reading devices), optical disk file devices, etc. that encode and transmit image information at high speed. This invention relates to a change point detection circuit.

(B) Conventional technology Since image information has a large amount of data (C pit count) compared to coded information such as character information, a method is used in which it is converted into coded data and transmitted in a compressed form. As one method, Recommendation T4 of 00 ITT (International Telegraph and Telephone Advisory Committee) recommends the MH (Modi/ad Hu//man) system as a one-dimensional encoding system for facsimile machines.

This method uses continuous black i! This is a method of data compression by counting the number of white pixels (hereinafter referred to as binary data) or white pixels (hereinafter referred to as O for binary data) and generating code data according to that number. .

Conventionally, as a method for realizing this method, as shown in Fig. 4,
Continuous image information signals are input into the input port of a microcomputer (incorporated) after being converted into parallel signals (in units of 1 byte (8 bits), for example) by a serial/parallel conversion circuit, and then converted into continuous O or The method used was to count the amount of data (pixels) of 1, read code data corresponding to that value from the encoded ROM (memory for continuous reading) @4, and output it to the output port of the microcomputer (incorporated). . In addition, as shown in Figure alE5, the image information signal from the image information source D is put into the shift register □□□, and the clock with the same speed as the shift clock from the clock source is used as the counting clock of the bit counter. The bit counter is then used as a change point detection circuit to detect the change point where the data changes from O to 1 or from 1 to O.FcO19 continues to count the data of 1 until the output is obtained. . Thereafter, a method has been adopted in which coded data corresponding to the value of the bit counter (b) is read out from the encoding ROM f4, and the coded data compressed as serial data by a parallel-to-serial conversion circuit is taken out.

(c) Problems to be Solved by the Invention These conventional methods cannot perform high-speed encoding due to rounding, where the code speed depends on the instruction execution speed of the microcomputer or the speed of the shift clock of the shift register. There was a drawback that it was difficult to do.

The present invention aims to provide a change point detection circuit that can quickly detect a change point in binary data.

4. Means for Solving the Problems The present invention provides methods for transmitting image information from an image scanner, optical disk file, etc. to a host computer, etc.
A serial-to-parallel conversion circuit that inputs serial binary data and simultaneously outputs data consisting of n bits per unit at fixed timings is used to reduce transmission time by performing MH encoding at high speed. The first to nth latch circuits (n is a positive integer greater than or equal to the second) into which one unit of data simultaneously output from the parallel conversion circuit is input bit by bit, and the (nth) latch circuit into which the 1LAN latch circuit output is inputted. -1-+) latch circuit, first and second latch circuit outputs, second and third latch circuit outputs, ..., the (
n-1) and the n-th latch circuit output, and the n-th and (n+1)-th
) first to (n-H) with two latch circuit outputs each! ! 1XOR circuit.

(E) Operation Since the present invention is configured as described above, it is possible to determine whether or not there is a change point in one unit of data, as well as between the last bit of the immediately preceding data and the first data of the data. Can be detected instantly. The presence or absence of this change point is detected, the number of data until the change point occurs is counted, and code data of the MH system can be selected based on the counting result.

(f) Embodiment FIG. 1 is a schematic configuration diagram of an image information transmission device equipped with the circuit of the present invention, FIG. 2 is a circuit diagram of a main part of an embodiment of the circuit of the present invention, and FIG. FIG.

In FIG. 1, [1] is the encoded data source;
For example, it reads image information on a document and serially outputs digital data based on this image information.

(2) is a serial-to-parallel conversion circuit that inputs the serial binary data from this encoded data generation source (11), which consists of one unit of n bits (n-1 in the example) at each fixed timing. Data is simultaneously output to n output terminals.

(3) is a change point detection circuit which inputs the 8-bit parallel data from the serial-to-parallel conversion circuit (2), and detects whether or not there is a change point in the 8-bit data input at each specified timing. and a change point detection unit (4) that outputs data indicating the position of a change point (details of this detection unit will be described later with reference to FIGS. 2 and 5); It includes a pixel number conversion circuit (5) that converts the data number from 4) into the number of pixels, and an addition circuit (6) that inputs the output of the conversion circuit (5).

The output of this adder circuit (6) is the encoded data generation source (1
It represents information related to the number of bits from one change point to the next change point in serial binary data output from 1, and is output regardless of the occurrence of a change point.

When the adder circuit (6) generates an output, a trigger for forming a second clock signal is input to a second clock signal forming circuit, which will be described later. (7) is an encoding ROM that receives the output of the change point detection circuit (31), which holds the code data of the MH system, and the code data C00ITT corresponding to the input adder circuit (6) output. (as indicated by recommendation T4). (8) is a parallel-to-serial conversion circuit that converts code data from this encoding ROM (71) into serial data, (9) is a transmission processing means for transmitting serial code data, and a [a] represents each of the above circuits. This is a control circuit that controls the

In such an image information transmission device, the distance between the change points of encoded data based on image information from the encoded data source (source) is counted, and based on the distance, the encoded data is compressed and converted into MH code and transmitted. It is transmitted to processing means (9). Therefore, high-speed transmission of image information becomes possible.

Next, the change point detection section will be explained with reference to FIGS. 2 and 3. (Atl~(AIl) is the first to nth
This is a latch circuit, and each latch circuit is composed of a D flip-flop.

The first output terminal of the serial-to-parallel conversion circuit (2) is connected to the D input terminal (B+) of the first latch circuit (A1). Similarly, the second output terminal of the conversion circuit (2) is connected to the D input terminal (B2) of the second latch circuit (A2).
The fifth to nth output terminals of the conversion circuit (2) are connected to the third to first output terminals CBS) to (Bn) of the latch circuits (A5) to (An).

(A111(1) is the (n+1)th latch circuit, and the output of the nth latch circuit (An) is given to the D input terminal (Bn+1) of the D flip-flop that constitutes this latch circuit.

First to (n+1) latch circuits [A1] to (An+
1) is connected to each input terminal as shown in Figure 3.
P) is given, and the n-bit data from the serial-to-parallel converter circuit (2) and the n-th latch circuit output data are simultaneously taken in every fixed period C time T), and at the same time, the data of the D input terminal at that time is Data (1 or 9 is O) is output to the Q output terminal.

(Of) ~ (○n+1) is the first without the first [n+1]E
The first EXOR circuit (c+) is the first
and the outputs of the second latch circuit (AI) (input 2) are 2 inputs, and the second BXOR circuit (02) is 2 inputs each of the outputs of the second and third latch circuits (At)rA3), and so on. In addition, the n1-th n+1) and the first latch circuit (An+L, >t(-A
Each output of the axis) is assumed to be two inputs. Therefore, the first to nth
1XOR circuit (01) ~ (On) each output terminal (DI)
~(Dn) has the first to nth latch circuits (A1)~
Among the bit data input to (An), when there is a change between adjacent data, a high level output is produced. In addition, the output terminal (Dtx+1) of the (n+1)th HXOR circuit c(n+1) has a high level when there is a change between the last bit of the previous n-bit data and the first bit of the current n-bit data. The output is as follows.

(B 1 ) ~CBrx-1) and (Iiin+1
) are the first to (n-1)th and (n+1)th BXOR
An inverter that receives each output of circuits (01) to (On-1) and (On+1) as input, and each inverter (El) to (E
n-1) and (Kn+1) perform a significant operation as an inverter when the Q output of the D flip-flop, which will be described later, is at the a9 level, and on the other hand, when the Q output is at a high level, the operation as an inverter is disabled and always It exhibits a high level output.

(Fl) to (Fn) are first to n-th AND gates, which are used to determine priorities for the outputs of the first to first EXOR circuits (01) to (On). The first ant game) (Fl) is the (n-H) BXOR circuit (On+1
) connected to the inverter (En+1) output and the 1st E
The output of the XOR circuit (01) is used as 2 inputs, and the second ant game is
) (F2) is the inverter (En-H) output and the second
The inverter (El) connected to the EXOR circuit (01)
) output and the second EXOR circuit (02) output as 5 inputs,
Similarly, the n-th AND gate (Fl11) is connected to the first to (n-1) EXOR circuit (011 to C(n-1) outputs) and the inverter (El) to (En-1) outputs and the first EXOR (circuit (On) output) are input.

(G1) to (Gn-+) are the first to (n-t
)D flip-flop C is denoted as flip-flop iFF), and (Gn+1) is the (n+t)th pF
It is F. The first DFF' (G1) is the first AND gate (
Ft) is received at the D input terminal, and the second output is received at the T input terminal.
When receiving the second clock signal from the clock signal forming circuit TILL, it outputs the data at the D input terminal to the Q output terminal, and outputs its inverted data to the Q output terminal. The Q output terminal output is given to the control terminal (Hl) of the inverter (El), and the output terminal output is given to the other input of the AND gate CJ1) which has the first ant gate (Ft) output as one input. nru. Similarly, the second DFF (G2) to the (n-1)th DFF (Gn-+) receive the output iD input terminal of the second to (n-1)th DFF, respectively, and the second DFF (G2) to the T input terminal. When receiving the second clock signal from the a-clock signal forming circuit C11l, it outputs the data at the Q input terminal to the Q output terminal, and outputs its inverted data to the stone output terminal. Each Q terminal output is connected to each control terminal (H2) of the second to (n-1) inverters (E 2 , ) to (En-1).
〜(Hn-1), and the output from the 2nd to (n-1)th output terminal is an AND gate (Jri〜(Jn- 1)
is attached to each other input. No. (n-H) D P
F (Gn+1) is the (n+1)th EXOR circuit (On
-N) is received at the D input terminal, and the T input terminal receives the second clock signal from the second clock signal forming circuit αυ. Just in case, the data at the D input terminal is output to the Q output terminal, and Output the inverted data to . The Q output terminal output is the control terminal (Hn+) of the inverter (En+t) to which the output of the (n+1)th EXOF1 circuit (On+1) is applied.
1), and the mutual output terminal output is the (n+1)th g
X.

Ant game with 8 circuit (On+t) output as one input
) (Jn-N) is applied to the other input. Each of the above DFFs is reset immediately before the generation of the a-check signal (OP), but its configuration is not shown. The first to (n+1)th output terminals (K1) to (Kn+1) receive the output of the AND gate (Jl) to Jn+1), and each output terminal receives the n input to the change point detection section (4). There is no change point in the bit data, and this n
If the first bit of the bits matches the last bit of the previous n bits, a low level output is provided. If there is a change point in the input data, a high level output is output to the output terminal corresponding to the change point with a high priority.
Signal processing based on this high-level output is executed by the adder circuit (6) at the subsequent stage. The second clock signal forming circuit α11 receives the trigger generated after this signal processing.
rNL@cn-1) OFF' (G 1 ) ~(G
n-1) and gg(n+1) D F F (Gn+
1) A trigger is applied to the T input terminal to invert the output terminal corresponding to the next priority level to high level and invert the output of the previous high level output terminal to low level.

Next, the operation of this change point detection section (4) will be explained in a little more detail. First to nth latch circuits (A1) to (An)
Each time a clock signal (OP) is generated, each input terminal of
First, second, third, . . . n-bit data of input data are input. That is, as shown in FIG. 3, as nm8, data (Mz) (M2) (Ms) - is given to the first byte, second byte, and so on every time a clock signal is generated.For explanation, The first byte of data is (000
00000), and the second byte data is (1111
1100), and the third byte of data is (111
11101).

The first to n-th latch circuits (A1) to (An) receive the first clock (CPI) Q, take in 10# data to the D terminal of each latch circuit, and simultaneously output 10# data to the Q output terminal.
Output. At this time, since there is no change point between adjacent data, the outputs of each EXOR circuit (01) to (On) are all 10#, and the output terminals (K1) to (Kn) are also 10#.
#Output wo. The adder circuit (6) counts and holds that 10# continues for 8 bits.

Next, the second clock (OP2) is received and the second clock is applied to the D input terminals of the first to n-th latch circuits (A1) to (An).
Import byte data. As a result, 10# is applied to the Q output terminals of the first and second latch circuits (At) (A2), and the third to nth (i.e., eighth) latch circuits (As
) to (An) outputs l111# to the Q output terminals.

Note that since the most significant bit of the first byte of the (n+1)th latch circuit (An+1) is 1101, 0# is output to its Q output terminal. The Q output of the second latch circuit (A2) is %011, and the Q output of the third latch circuit (AI) is 111.
', only the output of the second EXOR circuit (02) (7) becomes 911'. As a result, the second Antogame) (F
'? ) The output becomes J#, and '1# is given to the D input terminal of the second DFF' (G2), and the AND gate (J2)
11# is given to the output terminal (F2) of the AND gate (see FIG. 3 (Nt)).

When the adder circuit (6) sees that this output terminal (F2) exhibits 111#, it recognizes that 10' continues up to the second-order bit of the second byte, and stores the code in the encoding ROM (71). 10# gives a signal 4+ for extracting a code corresponding to 1D pit continuous data from the conversion ROM.At the same time, it indicates that this adder circuit (6) has completed one change point detection process. A trigger is applied to the second clock signal forming circuit αυ. Upon receiving this trigger, the second clock signal forming circuit αυ converts the first to (n-1)th DFFs (G
l ) to (Gn-t) and the (n+1)th DFF (Gn-
N) to each T input terminal Nidorica (tl) t-. Each DFF applies the D input data to each Q output terminal at the time of this trigger input, and as a result, the inverter I CHt ) control 11
The inverter operation of the nuclear inverter becomes impossible when m child (H2HC'J' is applied. As a result, this inverter (
5th to nth anime games) (Fs) to (F2) by (F2)
Since there is only a change point between the 2nd bit and the 3rd bit in the F2th byte, only one change point detection process is performed in the second clock period (T2). Then, the adder circuit (61 [from the 3rd bit of the 2nd byte to the 8th bit of I!f)
Continuation of 1# is counted and held. Before inputting the third clock (CF2), the first to (n-th
t) DF'F (G1) ~ (Gn-%) and (n+t
) DF F (Gn+t) is reset.

Subsequently, in response to the third clock (OPI) 1, the first to nth latte circuits (A1) to (An) output the third byte of data (first) to each Q output terminal. It exhibits an output of 111 or %011 according to . 1st RXOR
Circuit 01) has 2 inputs wAll-c and an output of 1
0#, 21st eXOR time M(02) is 11" and %ol
Since the t- input is input, the output is "1". Similarly, the third RXOR circuit (Os) inputs 10" and 11#, so the output is 11.
1'. Furthermore, since the fourth to (n-H) EXOR circuits (04) to (On (1) each have two inputs of 11', each output becomes 10".

Since the output of the first HXOR circuit [01] is 101, the output terminal (K1) is %(311), and since the output of the second gXOR circuit (C2) is 111, the output terminal (F2) is 1.
1'. The third EXOR circuit (Os) output is °'1"
However, the period during which the inverter (F2) is effective (second
DFF (period in which the Q output of ()2) is 101) closes the third ANDG (F5), so the output terminal (
Kl) becomes '0''.The other output terminals are all 10# because the corresponding EXOR circuit output is 10#.

The operation due to the output of the output terminal (F2) being 111 is substantially the same as described above. However, the addition circuit (6
) counts 7, which is the sum of the bit number 6 of the second byte data 11" and the bit number 1 of the third byte least significant bit 11#, and 11# from the encoded ROM (7) is 7. A code corresponding to data of consecutive bits is output. After this addition processing operation is completed, a trigger is given to the second clock signal forming circuit qv, and the second clock signal (t2) is outputted from the first to (n-1) clock signals. DF'F and the T input terminal of the (n-H) DFF.As a result, the Q of the second OFF (Gz)
An inverter with an output terminal of 11" (
F2) inverter operation is disabled. As a result, the closed state of the inverter (F21 output) of the third AND gate (FB) is released, and the output terminal (KM) is changed from 10" to 1".
1".The adder circuit (6) outputs this output terminal (K
3) receives the data Jl from the encoded ROM (71 to 1
A signal is output to be processed so as to extract a code corresponding to one 01. After this addition process, the second clock signal (t
3) and check the state of the latch circuit output after that. Since all subsequent output terminal outputs are 10#, it is recognized that the 6 bits from the 5th bit to the 8th bit are 11'' and held.

(G) Effects of the Invention The present invention provides a serial-to-parallel conversion circuit that inputs serial binary data and simultaneously outputs data consisting of one unit of n bits at every fixed timing, and a system that converts data that is simultaneously output from the serial-to-parallel conversion circuit to First to n-th latch circuits into which one unit of data is simultaneously input bit by bit; an (n-N)-th latch circuit into which the n-th latch circuit output is input; first and second latch circuit outputs; and third latch circuit output,
..., the (n-1)th and nth latch circuit outputs, and the nth
and the first to (n+1)th BX OR circuits each having two inputs of the output of the (n+1)th latch circuit.
The point of change in bit data (the point of change from 0 to 1 or from 1 to 0) can be instantly found, and the time required to discover this point of change can be saved.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of an image information transmission device equipped with the circuit of the present invention, FIG. 2 is a circuit diagram of a main part of an embodiment of the circuit of the present invention, and FIG. 3 is a time chart diagram for explaining the operation of the circuit. , FIG. 4, and FIG. 5 are configuration diagrams of different conventional examples. (2) Serial-to-parallel conversion circuit, (AI)
~(An)...first to nth latch circuits, (An+
1)-#J(n+1) latch circuit, (01)~(
On+1) -・First to (nl) RXOR circuit

Claims (1)

[Claims] (1) A serial-to-parallel conversion circuit that inputs serial binary data and simultaneously outputs data consisting of n bits per unit at a certain timing, and converts one unit of data that is simultaneously output from the serial-to-parallel conversion circuit bit by bit. The first to n-th latch circuits input at the same time, the (n+1)th latch circuit to which the n-th latch circuit output is input, the first and second latch circuit outputs, the second and third latch circuit outputs, etc.
・A first circuit with two inputs each being the (n-1) and n-th latch circuit outputs and the n-th and (n+1)-th latch circuit outputs.
A binary data change point detection circuit comprising: or (n+1)th EXOR circuit.