JPS63131612A - Signal detection circuit - Google Patents

Abstract

PURPOSE:To eliminate only noise by outputting AND of two outputs obtained through the comparison between an output of an integration circuit and an output of a level detection hold circuit. CONSTITUTION:A signal subjected to a constant time delay is inputted to two comparators 12, 13 using the output of the integration circuit 9 having a larger time constant than the pulse width of the signal to be detected and the output of a level detection hold circuit 11 generating a DC signal in response to the signal pulse level and holding it for a prescribed time as the threshold values. Since the output of the integration circuit 9 causes a DC voltage corresponding to the mean power of a consecutive noise, the consecutive noise is eliminated in the comparator 12 giving a threshold level and outputs of the comparators 12, 13 are ANDed to eliminate the residual noise respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a signal detection circuit that removes noise contained in an input signal.

[Prior art]

Electrical signals inherently often contain various noise components, and a signal obtained via a signal means, whether wireless or wired, is likely to contain a large amount of noise.

Various signal detection circuits have been proposed in the past to remove these noises and extract only the necessary signals. Figure 6 is a circuit diagram showing a conventional signal □ detection circuit. This is to remove noise and extract only what is necessary.

This signal detection circuit uses a comparator 2 to compare the input signal amplified by the amplifier 1 with a threshold level set by adjusting the resistor R. Anything below the threshold level is noise, and anything above it is noise. It is output as a necessary signal.

Although this signal detection circuit has the advantage of having a simple configuration, it has the disadvantage that if noise exceeding the threshold level is included in the signal, it will be output as shown in FIG.

In order to compensate for this drawback, conventionally, as shown in FIG. 8, the output of the amplifier 1 is branched and one of them is inputted to the integrating circuit 3, thereby obtaining a DC signal that increases or decreases depending on the signal level including noise. A configuration has been devised in which the other branched output of the amplifier 1 is input to the comparator 2.

According to this circuit, as the average power of the noise level included in the signal increases, the output of the integrating circuit 3 input to the negative pole of the comparator 2 increases, so these noise signals are removed and only the signals exceeding this are compared with the above-mentioned comparison. is obtained at the output of device 2.

However, as shown in FIG. 9, although this method is extremely effective in removing the noise N that is input immediately after the regular signal, such as the echo human input signal that frequently occurs in transponders or radars, the regular signal S2 is There is a defect in that when inputting the signal relatively close to the higher level signal S1, this normal signal S2 is also removed.

[Purpose of the invention]

The present invention was made to eliminate the defect of conventional signal detection circuits that also remove necessary signals, and an object of the present invention is to provide a signal detection circuit that can remove only noise.

[Summary of the invention]

In order to achieve the above object, the present invention adopts the following configuration.

That is, the output of an integrator circuit having a time constant larger than the pulse width of the signal to be detected and the output of a level detection hold circuit that generates a DC signal corresponding to the signal pulse level and holds it for a predetermined time are thresholded. The signal delayed by a certain period of time is input to two comparators to be held, and the AND of the output signals of the two comparators is calculated.

〔Example〕

Hereinafter, the present invention will be described in detail based on the illustrated embodiments.

FIG. 1 is a block diagram showing an embodiment of the signal detection circuit of the present invention.

In the figure, 5 and 6 are antennas and receiving circuits connected to the antennas, and this embodiment shows a case where noise is removed from a pulse signal that is a demodulated output of a radio receiver, and signal detection in this case. The circuit 7 is constructed as follows.

That is, the output of the receiving circuit 6 is input in parallel to each of the integrating circuit 9, the delay circuit 10, and the level hold circuit 11 via the amplifier 8, and the output of the integrating circuit 9 and the output of the delay circuit 10 are input in parallel to each other. 1 comparator 12 and delay circuit 1
The output of 0 and the output of the level hold circuit 11 are respectively input to the second comparator 13, and the two signals obtained are sent to the AND circuit 1.
4 and outputs the output of the AND circuit 14 as a desired signal.

The time constant τ of the integrating circuit 9 is set larger than the pulse width of the signal to be discriminated, and the level hold circuit 1
1 holds, for example, 80% of the amplitude value of the signal pulse for a certain period of time and outputs it.

The operation of this circuit will be explained below using the drawings.

FIGS. 2(a) to 2(f) show the output of the amplifier 8 and the input/output waveforms of the first comparator 12 and the second comparator 13. FIG. 4A shows an output waveform of the amplifier 8, which is assumed to include echo noise Ne and comparatively large-amplitude noises nl and n2 in addition to the regular signals Sl and S2.

First, when this signal passes through the integrating circuit 9, a DC voltage is generated in which continuous components in the signal, that is, noise components are accumulated, as shown by the broken line in FIG. 2(b), and the desired signals Sl, S2 and echo noise are generated. The integrating circuit 9, which has a time constant larger than the width of these pulses, does not act on pulses that are generated discretely.

The waveform shown in FIG. 2(b) shows the waveform appearing at the output of the delay circuit 10, and as is clear from the comparison with the waveform in FIG. 2(a), it is delayed by a time t.

On the other hand, when the signal is input to the level hold circuit 11, a voltage of approximately 90% of the pulse signal level is held for a predetermined time and output, resulting in a shape as shown by the broken line in FIG. 2(C).

That is, the hold voltage that has become VS+ due to the signal S1 exceeding the threshold level vh decreases after a certain period of time, but if the echo noise Ne arrives before it has completely decreased to the threshold level, the hold voltage remains unchanged. is held, and after the echo noise Ne pulse passes, the hold voltage decreases again. When the signal pulse S2 is subsequently input, the hold voltage rapidly rises to 90% of the level of the signal pulse S2, and after holding this value for a certain period of time, decreases to the threshold level. If prominent pulse noises persist, the hold voltage will respond to them as well.

The three signals obtained through the above process are each sent to the comparator 12.1.
3, in the former case the output of the delay circuit 10 exceeds the output of the integrating circuit 9, that is, the output of the delay circuit 10 (FIG. 2(d)), and in the latter case, the output of the delay circuit 10 exceeds the output of the level hold circuit 11. In other words, as shown in the figure (f), only the portion that exists in common in both signals is extracted and the desired signal pulse is Only S1 and S2 can be discriminated.

In other words, as is clear from FIG. In this case, the continuous noise can be removed.

Furthermore, although the comparator 13 which uses the voltage obtained by the level hold circuit 11 as a threshold level can remove echo noise that is relatively close to a normal signal and whose level is small, it stands out from other noise levels. Although pulse noise cannot be removed and remains, it is easy to understand that if the outputs of the two comparators 12 and 13 are ANDed, the remaining noise will be removed.

FIG. 3 is a circuit diagram showing a specific example of the level hold circuit 11.

In the figure, Q+, Qz, and C4 are FETs, C3 is a transistor, R3 to R6 are resistors, and CI+Cf is a capacitor.
When a pulse signal is input to the gate of FET, a drain current flows through resistor R1 in accordance with the pulse amplitude.
Since the drain potential of Q I decreases, the transistor Q
is turned on, and a high potential is applied to the connection point between the gate of FETQz and the resistor R4+RS via its collector.

Accordingly, the F ET Q z is turned on, so that the drain current of the F ET Q + stops flowing, and the transistor Q is also turned off.

However, a high potential is accumulated in the capacitor C2 connected to the gate of the FET Qa and the ground via the resistor R3, and the collector of the transistor Q and the FET
The gate of Qz and resistor R4 are both .

Since it exhibits a high resistance value, the FE 74 is in an on state for a predetermined period of time, and a high potential is generated at the output terminal during that time.

The discharge circuit connected to the gate of FETQa is for short-circuiting and discharging the accumulated charge in the capacitor Ct as necessary, and when the regular pulse signal interval is clear, the hold voltage is set to the threshold in synchronization with this. It is made to hang down to the shield level.

Note that the level hold circuit is not limited to this example.

Signal detection circuit 70 level hold circuit 11 shown in FIG.
can be considered to hold the gain level of the receiving circuit 6, so by feeding it back to the receiving circuit 6, it can be used as a gain control signal. Furthermore, since the output level of the integrator circuit 9 becomes high when there is a lot of continuous wave noise, it does not require any special explanation that this output may be used as a noise detection signal to drive the noise alarm circuit 15. Will.

FIG. 4 is a diagram showing a modified embodiment of the present invention, in which an integrating circuit 9 and a level hold circuit 1 of the signal detection circuit shown in FIG. 1 are shown.
The output of the integration and level hold circuit 11 is as shown in FIG. 5(a).
The waveform becomes the same as that shown in FIG.
The necessary signal Sl shown in the same figure (C) is compared with the output of
Only S2 can be detected.

In carrying out the present invention, it is not necessary to limit it to the embodiments described above, and it can be applied not only to wireless communication but also widely as a signal discriminator and a noise removal circuit.

〔Effect of the invention〕

Since the present invention is constructed as described above, it is effective in removing continuous noise, echo noise, etc., and detecting only necessary signals.

[Brief explanation of the drawing]

1 to 5 show embodiments of the present invention, in which FIG. 1 is a block diagram of a receiver having a signal detection circuit, and FIGS. 2(a), (b), (C1, (d), (
e). (f) is an input/output waveform diagram of each circuit in FIG. 1, FIG. 3 is a circuit diagram showing a specific example of a level hold circuit, FIG. 4 is a block diagram showing another embodiment of the present invention, and FIG. The figure shows the input/output waveform diagram of the block diagram in Figure 4, Figures 6 to 9 show conventional examples, Figures 6 and 8 are block diagrams of the signal detection circuit, and Figure 7 shows the block diagram of the signal detection circuit. This figure is an output waveform diagram of the signal detection circuit of FIG. 6, and FIG. 9 is an output waveform diagram of the signal detection circuit of FIG. 8. 1, 8-----------Amplifier 2,
12. 13. 16-・-・----Comparator 3
, 9−−−−−−−−−−−−・Integrator circuit 7−・
−1−−−−−−・−・Signal detection circuit i o −−−−
−−−−−−−−・・Delay circuit 11−−−−−・−・−
-1--Level hold circuit 14--------
−・−・Logic product circuit agent Patent attorney Katsuya Takayama Figure 1, 15 Figure 2 Figure 6 Figure 7

Claims (1)

[Claims] It includes an integrating circuit having a time constant larger than the pulse width of the desired signal, a delay circuit that delays the signal for the required time, and a level detection hold circuit that generates a DC signal according to the desired signal level and holds it for the required time. . A signal detection circuit characterized in that the signal detection circuit is configured to output a logical product of two outputs obtained by comparing the output of the integration circuit and the output of the level detection and hold circuit.