JPS63131230U

JPS63131230U -

Info

Publication number: JPS63131230U
Application number: JP1897887U
Authority: JP
Priority date: 1987-02-12
Filing date: 1987-02-12
Publication date: 1988-08-26

Description

[Brief explanation of the drawing]

第１図は本考案による２値化回路の一実施例を
示す図、第２図イは信号波形図、第２図ロは全波
整流波形図、第２図ハは２値化信号波形図、第３
図は光カードの記録再生の一例を示す図で、同図
イは平面図、同図ロは断面図、第４図はカードの
移動速度を示す図、第５図は従来の２値化回路を
示すブロツク図、第６図は第５図の２値化回路に
より得られる信号波形図である。１……光カード、２……記録再生トラツク、３
……ヘツド、Ｘ，Ｙ……走査方向、Ａ，Ｂ……加
速終了又は減速開始位置、Ｒ_１〜Ｒ_１０……抵抗
、Ｃ……コンデンサ、Ｄ_１，Ｄ_２……ダイオード
、ＺＤ……ツエナーダイオード、Ａ_１，Ａ_２……
演算増幅器、Ｃ_１，Ｃ_２……コンパレータ、Ｌ_１……ＡＮＤゲート、１１……全波整流回路、１２
……積分回路、１３……ゼロクロスコンパレータ
。 Fig. 1 is a diagram showing an embodiment of the binarization circuit according to the present invention, Fig. 2 A is a signal waveform diagram, Fig. 2 B is a full-wave rectification waveform diagram, and Fig. 2 C is a binarization signal waveform diagram. , 3rd
The figure shows an example of recording and reproducing an optical card, in which A is a plan view, B is a cross-sectional view, Fig. 4 is a diagram showing the moving speed of the card, and Fig. 5 is a conventional binarization circuit. FIG. 6 is a signal waveform diagram obtained by the binarization circuit of FIG. 5. 1... Optical card, 2... Recording and reproducing track, 3
...Head, X, Y...Scanning direction, A, B...Acceleration end or deceleration start position, _R1 to _R10 ...Resistor, C...Capacitor, _D1 , _D2 ...Diode, ZD... Zener diode, A ₁ , A ₂ ...
Operational amplifier, C ₁ , C ₂ ... Comparator, L ₁ ...AND gate, 11...Full wave rectifier circuit, 12
...Integrator circuit, 13...Zero cross comparator.

Claims

[Scope of utility model registration request]

an AC-DC converter that full-wave rectifies the signal input;
an integrating circuit that integrates the converter output; a comparison circuit that compares the integrating circuit output with a reference value and produces an output when the integrating circuit output is greater than the reference value; and a high level when the signal input is positive and a high level when it is negative. 1. A binarization circuit comprising a zero-cross comparator that outputs a low-level rectangular wave signal, and gate-controls the output of the zero-cross comparator using the output of the comparison circuit.