JPS63129383U - - Google Patents
Info
- Publication number
- JPS63129383U JPS63129383U JP2154687U JP2154687U JPS63129383U JP S63129383 U JPS63129383 U JP S63129383U JP 2154687 U JP2154687 U JP 2154687U JP 2154687 U JP2154687 U JP 2154687U JP S63129383 U JPS63129383 U JP S63129383U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- latch
- tally
- data
- switching pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000284 extract Substances 0.000 claims 1
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
Landscapes
- Studio Circuits (AREA)
Description
第１図は本考案のスイツチヤ制御回路の一実施
例のブロツク図、第２図は第１図のＶパルス検出
回路の実施例を示す回路図、第３図は従来のスイ
ツチヤ制御回路のブロツク図である。
１……インターフエース部、２……切替データ
、３……ストローブ信号、４……タリーデータ、
５……Ｖパルス、６……スイツチヤ制御部、７…
…ラツチ回路、８……ラツチ・デコード回路、９
……タリー選択回路、１０……Ｖパルス検出回路
、１１……入力端子、１２……時定数設定素子、
１３……マルチバイブレータ、１４……出力端子
、１５……スイツチヤ制御部。
Fig. 1 is a block diagram of an embodiment of the switcher control circuit of the present invention, Fig. 2 is a circuit diagram showing an embodiment of the V-pulse detection circuit of Fig. 1, and Fig. 3 is a block diagram of a conventional switcher control circuit. It is. 1...Interface section, 2...Switching data, 3...Strobe signal, 4...Tally data,
5...V pulse, 6...Switcher control section, 7...
...Latch circuit, 8...Latch decode circuit, 9
... Tally selection circuit, 10 ... V pulse detection circuit, 11 ... Input terminal, 12 ... Time constant setting element,
13... Multivibrator, 14... Output terminal, 15... Switcher control unit.
Claims (1)
フするスイツチヤ制御に対するデータラツチを行
う第１のラツチ回路と、この第１のラツチ回路の
出力を垂直帰線期間に同期して最終出力データの
ラツチ・デコードを行う第２のラツチ回路と、前
記スイツチヤ制御に対する応答を表すタリーデー
タを前記第１のラツチ回路の出力から取出して返
送するタリー選択回路とを有するスイツチヤ制御
回路において、垂直帰線期間切替パルスの有無を
検出する回路を有し前記垂直帰線期間切替パルス
の検出が無い場合には前記タリーデータの返送を
抑止する手段を備えて成ることを特徴とするスイ
ツチヤ制御回路。 A first latch circuit performs data latch for switch control that turns on and off broadcast video signals at video cross points, and the output of this first latch circuit is synchronized with the vertical retrace period to latch and decode final output data. In a switcher control circuit having a second latch circuit that performs switching, and a tally selection circuit that extracts and returns tally data representing a response to the switch control from the output of the first latch circuit, the presence or absence of a vertical blanking period switching pulse is determined. 1. A switcher control circuit comprising: a circuit for detecting the vertical retrace period switching pulse; and means for suppressing return of the tally data when the vertical retrace period switching pulse is not detected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2154687U JPH057819Y2 (en) | 1987-02-16 | 1987-02-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2154687U JPH057819Y2 (en) | 1987-02-16 | 1987-02-16 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63129383U true JPS63129383U (en) | 1988-08-24 |
| JPH057819Y2 JPH057819Y2 (en) | 1993-02-26 |
Family
ID=30818085
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2154687U Expired - Lifetime JPH057819Y2 (en) | 1987-02-16 | 1987-02-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH057819Y2 (en) |
-
1987
- 1987-02-16 JP JP2154687U patent/JPH057819Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH057819Y2 (en) | 1993-02-26 |