JPS63124533A - Manufacture of semiconductor integrated circuit device - Google Patents
Manufacture of semiconductor integrated circuit deviceInfo
- Publication number
- JPS63124533A JPS63124533A JP61271171A JP27117186A JPS63124533A JP S63124533 A JPS63124533 A JP S63124533A JP 61271171 A JP61271171 A JP 61271171A JP 27117186 A JP27117186 A JP 27117186A JP S63124533 A JPS63124533 A JP S63124533A
- Authority
- JP
- Japan
- Prior art keywords
- film
- silicon oxide
- silicon
- oxide film
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 230000001590 oxidative effect Effects 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 1
- 229920005591 polysilicon Polymers 0.000 abstract description 13
- 230000003647 oxidation Effects 0.000 abstract description 10
- 238000007254 oxidation reaction Methods 0.000 abstract description 10
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 239000003990 capacitor Substances 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000004698 Polyethylene Substances 0.000 description 1
- 210000000988 bone and bone Anatomy 0.000 description 1
- HXNZTJULPKRNPR-UHFFFAOYSA-N borinine Chemical compound B1=CC=CC=C1 HXNZTJULPKRNPR-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000002178 crystalline material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- -1 polyethylene Polymers 0.000 description 1
- 229920000573 polyethylene Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置の製造方法に係り、骨に多
結、ｌ′＆シリコン膜にシリコン酸化膜を被着する製造
方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor integrated circuit device, and more particularly, to a method of manufacturing a semiconductor integrated circuit device, in which a silicon oxide film is deposited on a bone and a silicon oxide film.
従来、多結晶シリコン（ポリ・シリコン）膜にシリコン
酸化膜を被着する方法、例えばＩＴｒ −ＩＣ（１トラ
ンジスター１チヤネル）・ＭＯＳダイナミ、クラム（以
下Ｄ−Ｒ，ＡＭ）の容量プレートとワード線材との間の
絶縁膜として、容量グレートであるポリーンリコン＠／
Ｃシリコン酸化膜を被着する方法は、第４図、第５図忙
示される。すなわち、第４図において、半導体基板１１
上に１シリコン酸化膜１２，７１Ｊコン窒化膜１３の容
量絶縁膜が被着され、さらにその上部にリンなどが拡散
されたポリ・／リコンＲ１４が、フォト譬ンジスト膜１
５によっ℃、容量グレートにパターニングされている。Conventionally, a method of depositing a silicon oxide film on a polycrystalline silicon (polysilicon) film, for example, ITr-IC (1 transistor, 1 channel), MOS dynamic, CRAM (hereinafter referred to as D-R, AM) capacitor plate and word line material. As an insulating film between
The method of depositing the C silicon oxide film is shown in FIGS. 4 and 5. That is, in FIG. 4, the semiconductor substrate 11
A capacitive insulating film consisting of a silicon oxide film 12 and a 71J silicon nitride film 13 is deposited thereon, and a poly/recon R14 in which phosphorus or the like is diffused is further deposited on top of the capacitive insulating film 12, a silicon oxide film 12, and a silicon nitride film 13.
It is patterned to a capacitance grade of 5°C.
第５図において、第５図のフォト・レジスト膜１５を除
去した後、ポリ・シリコン膜１４を酸化して、／リコン
酸化膜１６を被着した。この後、シリコン窒化、’ｆｇ
１３ 、 シリコン酸化膜】２を除去して、ゲート
絶縁膜を被着し、ワ−ド線となるポリ・シリコン膜やク
リサイド材が被着され、従来の方法により、Ｄ−ＲＡＭ
が製造される。In FIG. 5, after the photoresist film 15 of FIG. 5 was removed, the polysilicon film 14 was oxidized and a silicon oxide film 16 was deposited. After this, silicon nitridation, 'fg
13. Silicon oxide film] 2 is removed, a gate insulating film is deposited, a polysilicon film and a crystalline material which will become word lines are deposited, and the D-RAM is fabricated using the conventional method.
is manufactured.
前述した従来のパターニングされたポリ・シリコン膜１
４にシリコン酸化膜１６を被着する際に、前記ポリノリ
コン膜１４で形成される容量グレート側面が、パターニ
ングされた！！ｌまの半導体基板表面と垂直に近い伏態
で、８量グレートとワード線材との絶縁性を高めるため
に厚＜（４０００Ｘ〜６０００ Ｋ ）酸化していたた
め、答量絶碌膜と容量グレートの端部付近がクサビ伏に
酸化され、′＆量グレート端が持ち上げられてしまう。The conventional patterned polysilicon film 1 mentioned above
When the silicon oxide film 16 was deposited on the silicon oxide film 16, the side surface of the capacitor grate formed by the polynolyric film 14 was patterned! ! It was oxidized to a thickness of <(4000X to 6000 K) in order to improve the insulation between the 8-capacity grating and the word wire in a lying state close to perpendicular to the surface of the semiconductor substrate. The area near the end is oxidized in a wedge-shaped manner, and the end of the grate is lifted up.
また、第５図にも示すように容重グンート地上部のクリ
コン酸化膜が厚く成長して、オーパーツ・ングになって
形状悪化や絶縁耐圧の劣化が生ずるという欠点があった
。In addition, as shown in FIG. 5, the oxidized silicon film on the ground surface of the grommet grows thickly, resulting in an overhang, resulting in deterioration of the shape and deterioration of the dielectric strength.
本発明の目的は、前記欠点を解決し、絶縁性が劣化しな
いようにした半導体集積回路装置の製造方法を提供する
ことにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device that solves the above-mentioned drawbacks and prevents deterioration of insulation properties.
本発明の半導体集積回路装置の製造方法の構成は、−導
１！型を有する半導体基板上に絶縁膜を被着する工程と
、前記絶縁膜上に多結晶シリコン膜を被着し、これに不
純物を拡散して導電性をもたせる工程と、前記多結晶シ
リコン膜を所望の形伏Ｋ Ａターニングする工程と、パ
ターニングされた前記多結晶クリコン膜を酸化してその
一部をクリコン酸化物に変える工程と、前記シリコン酸
化物を除去する工程と、前記多結晶シリコン膜を酸化し
、クリコン酸化膜を成長する工程とを含むことを特徴と
する。The structure of the method for manufacturing a semiconductor integrated circuit device of the present invention is as follows: -1! a step of depositing an insulating film on a semiconductor substrate having a mold; a step of depositing a polycrystalline silicon film on the insulating film and diffusing impurities into it to make it conductive; a step of turning the polycrystalline silicon film into a desired shape; a step of oxidizing the patterned polycrystalline silicon film to convert a part of it into a clicon oxide; a step of removing the silicon oxide; and a step of removing the silicon oxide. The method is characterized in that it includes a step of oxidizing and growing a cricon oxide film.
〔実施例Ｊ 次に本発明を図面を参照しながら拝絹に説明する。[Example J Next, the present invention will be explained in detail with reference to the drawings.
第１図、第２図は本発明の実施例の半導体集積回路装置
の整造方法を順次示す断面図である。まず第１図におい
て、半導体基板１上に、クリコン酸化膜２．シリコン窒
化膜３の各量絶嫌膜が被着゛され、その上部にＤ−Ｒ，
ＡＭの容量グレートとしてのポリ−シリコン膜４と絶Ｐ
＆膜として用いるクリコン酸化膜５が被着される。この
半導体基板１上に、シリコン酸化膜２．シリコン窒化膜
３及びリンなどの拡散されたポリ・シリコン膜４を被着
、容量グレートを形成する工程は、第４図に示す従来と
同様の方法を用いる。ただしポリ・シリコン膜４は、従
来方法よりも厚い膜厚＜ ４ｏｏｏ１乃至５ｏｏｏＸ）
で被着し、２度の酸化により容量グレートが薄くなり過
ぎないようＫする。FIGS. 1 and 2 are cross-sectional views sequentially showing a method of fabricating a semiconductor integrated circuit device according to an embodiment of the present invention. First, in FIG. 1, a silicon oxide film 2. A silicon nitride film 3 is deposited on each layer, and D-R,
Poly-silicon film 4 and absolute P as capacitance grade of AM
A cricon oxide film 5 used as a & film is deposited. On this semiconductor substrate 1, a silicon oxide film 2. The steps of depositing a silicon nitride film 3 and a polysilicon film 4 in which phosphorous or the like is diffused to form a capacitance grating are performed using the same conventional method as shown in FIG. However, the polysilicon film 4 is thicker than the conventional method (<4ooo1 to 5oooX)
It is coated with K to prevent the capacity grating from becoming too thin due to second oxidation.
第２図は、１回目の酸化を行なった後の断面図である。FIG. 2 is a cross-sectional view after the first oxidation.
酸化条件は、８５０℃乃至９５０℃、バーニシグ雰囲気
で、ポリ・シリコン膜上に１０００＾乃至２０００にの
膜厚でクリコン酸化膜が成長されるように酸化を行なう
。この時、酸化雰囲気にさらされる面積の大きいポリ・
シリコン膜４の上端部は、シリコン酸化膜６Ｋｆわり易
く、ボリンリコン膜４にはテーパーが付けられる。また
、この酸化により、ポリシリコン膜端が持ち上げられな
いように条件を設定する。この後、シリコン酸化膜６を
除去し、再び酸化を行なう。酸化条件は、紡回同様８５
０℃乃至９５０’Ｏ，バーニング雰囲気でポリ・シリコ
ン膜上に１５００Ｘ〜３０００λの酸化膜が被着される
条件で行なうことＫより、第１図に示した状態が得られ
る。この後、従来の方法によりＤ−ＲＡＭを構成する。The oxidation conditions are 850° C. to 950° C. in a burnishing atmosphere, and oxidation is performed so that a cricon oxide film is grown to a thickness of 1000° to 2000° C. on the polysilicon film. At this time, polyethylene, which has a large area exposed to the oxidizing atmosphere,
The upper end of the silicon film 4 is a silicon oxide film 6Kf, which is easy to break, and the borin silicon film 4 is tapered. Further, conditions are set so that the edges of the polysilicon film are not lifted up by this oxidation. Thereafter, silicon oxide film 6 is removed and oxidation is performed again. The oxidation conditions were 85% the same as for spinning.
The state shown in FIG. 1 is obtained by performing the process under conditions such that an oxide film of 1500X to 3000X is deposited on the polysilicon film in a burning atmosphere at 0 DEG C. to 950 DEG C. to 950 DEG C. Thereafter, the D-RAM is configured using conventional methods.
第３図は本発明の他の実施例の半導体集積回路装置の製
造方法を示す断面図である。同図において、半導体基板
７上に、素子分離部になるシリコン酸化膜８．１０．ポ
リ舎シリコン膜９が被着されている。本実施例では、ポ
リ・シリコン膜９を素子分離部に用いており、半導体基
板７に直接被着されたシリコン酸化膜８厚を、通常のＬ
ＯＣＯ８法よりも薄くしても、素子分離部寄生トランジ
スタのスレ７ヨルド電圧（ｖｔｈ 分離部）は低下し
ない。また、半導体基板７に直接被着したシリコン酸化
膜８厚を薄くできるため、装置が高い放射線密度で被ば
くしても、Ｓｉ ５ｉ０２界面にトラ、グされる電子
の量が、ＬＯＣＯ８法の素子分離に比べ、はるかに少な
くなり、ｖｔｈ分離部の変動（Ｎチャネル部では低下、
Ｐチャネル部では上昇）を小さくすることができる。FIG. 3 is a sectional view showing a method of manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention. In the same figure, silicon oxide films 8, 10, . A polysilicone film 9 is deposited. In this embodiment, a polysilicon film 9 is used for the element isolation portion, and the thickness of the silicon oxide film 8 directly deposited on the semiconductor substrate 7 is
Even if it is made thinner than the OCO8 method, the threshold voltage (vth isolation part) of the parasitic transistor in the element isolation part does not decrease. In addition, since the thickness of the silicon oxide film 8 directly deposited on the semiconductor substrate 7 can be reduced, even if the device is exposed to high radiation density, the amount of electrons trapped at the Si 5i02 interface can be reduced. Compared to
(increase) in the P channel portion can be reduced.
以上説明したように、本発明は、ポリ脅シリコン膜を酸
化し被着した酸化膜を除去した後、再び酸化することに
より、ポリ・クリコン膜の側端部に被着したシリコン酸
化膜がオーバ・ハング状態にならず、かつポリ・ノリコ
ン膜端部が持ち上げられることのない艮好な形状と信頼
性の高い絶縁耐圧が得られるという効果がある。As explained above, the present invention oxidizes the polycrystalline silicon film, removes the deposited oxide film, and then oxidizes it again, thereby overlapping the silicon oxide film deposited on the side edges of the polycrystalline silicon film.・It has the effect of providing an attractive shape and highly reliable dielectric strength without causing a hanging state and preventing the edges of the poly-silicon film from being lifted.
第１図、第２図は本発明の一実施例の半導体集積回路装
置の夷遣方法を順次示す断面図、第３図は本発明の他の
実施例の半導体集積回路装置の製造方法を示す断面図、
第４図及び第５図は従来法によるパターニングされたポ
リ嗜シリコン膜にシリコン酸化膜を被層する工程を順次
示した断面図である。
１．７，１０１・・−・・・半導体基板、２．５，６゜
８．１０．１春２．１＄６・・−・・・シリコン酸化膜
、３．１命３・・・・・・シリコン窒化膜、４．９．］
尋４・・・・・・ポリ・シリコン［、Ｉ Ｇ ５−−−
−・・フォト・レジスト膜。
代理人 弁理士 内 原 晋／ヅ・″“ゝ・（・
、 ・
（じ゛・1 and 2 are cross-sectional views sequentially showing a method for manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. 3 shows a method for manufacturing a semiconductor integrated circuit device according to another embodiment of the present invention. cross section,
FIGS. 4 and 5 are cross-sectional views sequentially showing the steps of coating a silicon oxide film on a patterned polysilicon film by a conventional method. 1.7,101...Semiconductor substrate, 2.5,6°8.10.1 Spring 2.1$6...Silicon oxide film, 3.1 Life 3... ...Silicon nitride film, 4.9. ]
Fathom 4...Poly silicon [, I G 5---
-...Photoresist film. Agent: Patent Attorney Susumu Uchihara／ㅅ・”“ゝ・（・
, ・ (ji゛・
Claims (1)
程と、前記絶縁膜上に多結晶シリコン膜を被着し、これ
に不純物を拡散して導電性をもたせる工程と、前記多結
晶シリコン膜を所望の形状にパターニングする工程と、
パターニングされた前記多結晶シリコン膜を酸化してそ
の一部をシリコン酸化物に変える工程と、前記シリコン
酸化物を除去する工程と、前記多結晶シリコン膜を酸化
し、シリコン酸化膜を成長する工程とを含むことを特徴
とする半導体集積回路装置の製造方法。a step of depositing an insulating film on a semiconductor substrate having one conductivity type; a step of depositing a polycrystalline silicon film on the insulating film and diffusing impurities therein to make it conductive; a step of patterning the film into a desired shape;
A step of oxidizing the patterned polycrystalline silicon film to convert a part of it into silicon oxide, a step of removing the silicon oxide, and a step of oxidizing the polycrystalline silicon film to grow a silicon oxide film. A method for manufacturing a semiconductor integrated circuit device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61271171A JPS63124533A (en) | 1986-11-14 | 1986-11-14 | Manufacture of semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61271171A JPS63124533A (en) | 1986-11-14 | 1986-11-14 | Manufacture of semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63124533A true JPS63124533A (en) | 1988-05-28 |
Family
ID=17496328
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61271171A Pending JPS63124533A (en) | 1986-11-14 | 1986-11-14 | Manufacture of semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63124533A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4987091A (en) * | 1989-01-23 | 1991-01-22 | Nec Corporation | Process of fabricating dynamic random access memory cell |
| US5306648A (en) * | 1986-01-24 | 1994-04-26 | Canon Kabushiki Kaisha | Method of making photoelectric conversion device |
-
1986
- 1986-11-14 JP JP61271171A patent/JPS63124533A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5306648A (en) * | 1986-01-24 | 1994-04-26 | Canon Kabushiki Kaisha | Method of making photoelectric conversion device |
| US4987091A (en) * | 1989-01-23 | 1991-01-22 | Nec Corporation | Process of fabricating dynamic random access memory cell |
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