JPS63123124A - Fuzzy inference engine - Google Patents

Abstract

PURPOSE:To process fuzzy information efficiently and at high speed by being equipped with an arithmetic circuit to combine two fuzzy propositions and/or operate respective ones and a changing-over circuit to select a combined arithmetic circuit in accordance with a combined selecting input. CONSTITUTION:In an extended fuzzy inference engine, an arithmetic circuit to combine two fuzzy propositions and/or operate respective ones and a changing-over circuit to select the combined arithmetic circuit in the combined selecting input are equipped. The extended fuzzy inference obtains the conclusion expressed as follows. Namely, when implication is x=A and/or y=B z=C and a premise is x=A and/or y=B, a conclusion comes to be z=C. The changing-over of the combination and/or of two fuzzy propositions which are x=A and y=B in the implication can be executed by a selecting input signal from the external part. Consequently, the wide inference can be achieved.

Description

[Detailed description of the invention] Summary of the invention Extended fuzzy inference.

Implications: x-A andlor y-B→Z-C Premises:
X-A-andlory-B-Conclusion:z-C
− It is a fuzzy inference engine that executes. The combination and10r of the two fuzzy propositions x=A, ym13 in the implication can be switched by an external selection input signal (FIG. 12).

(See Figures 19 and 20).

Background of the Invention The present invention relates to a fuzzy inference engine that is an essential component of a fuzzy computer, and in particular to a modus inference engine that includes an implication with two fuzzy propositions in the antecedent part.
Concerning an enhanced fuzzy inference engine that performs ponens.

The great human brain has the concept of stored programs,
We created a digital computer by harmonizing pool algebra and binary e-hardware with stable operation. This continuous operation has made it possible to develop deep logic and perform deep processing of data. Digital computers are highly reliable due to their stable operation, and digital computer systems are becoming increasingly large. As long as the program does not contain information on a human mental level, a digital computer can be programmed with anything, and in this respect it can even be called a general-purpose machine.

With the realization of digital computer systems, human life2 and society are undergoing major changes.

Another great human brain has studied what and how humans think and how they communicate with each other, and has created the extremely important concept of fuzziness. ■１
．． A. Zadeh proposed the concept of fuzzy sets in 1965. Since then, many papers have been published on fuzzy theory, but there are still few reports on its application, and the reality is that it has only been done with the help of binary digital computers.

In fuzzy research, a person's knowledge is based on accumulated experience that should be summarized with linguistic information, like the know-how of an expert. That is emphasized. This linguistic information is generally characterized by ambiguity, ambiguity, uncertainty,
It is characterized by incompleteness or inaccuracy and by a membership function. Membership size is 0
．． It is expressed by a numerical value in the range between 0 and 1.0,
It varies within this range.

When linguistic information is handled by digital computers, membership magnitude (values) are represented by binary codes. The values represented by this binary code are stored, transferred, and operated on in binary electronic circuitry over and over again according to the stored program. Therefore, there is a problem in that it takes a long time to process fuzzy information by digital systems. Additionally, binary-encoded values require an incredibly large number of storage and operation devices. Although digital computers are general-purpose machines as described above, they are not necessarily optimal for processing fuzzy information in real time. Here.

Fuzzy information can be processed efficiently and at high speed, etc.
3 - There is a need to explore types of machines.

SUMMARY OF THE INVENTION This invention provides a 7%-doware system, or "fuzzy computer", suitable for processing fuzzy information.
We aim to provide a fuzzy inference engine that is essential for the construction of a new system called, in particular, an extended fuzzy inference engine that executes a modus ponens that includes an implication with two fuzzy propositions in the antecedent part. purpose.

The present invention provides an arithmetic circuit that calculates the combination and/or of two fuzzy propositions in an extended fuzzy inference engine that executes a modus ponens that includes an implication having two fuzzy propositions in its antecedent part;
and a switching circuit that selects a combination calculation circuit in accordance with a combination selection input.

Extended fuzzy inference seeks a conclusion expressed as follows.

Implications: x-A andlor y-B-*z-C blemish:
x-A -andlor V-B -Conclusion
:z-C- The two fuzzy propositions xmA and y-B in the implication are connected by andlor or "and/or". For example, ``and/J'' is executed by a MIN operation, and ``or(orN'' is executed by a MAX operation.According to the present invention, switching of this combination ``and/or'' is made possible by an external selection input signal. As a result, a wider range of inferences can be achieved.

Description of examples 1. Fuzzy inference The simplest human rule of thumb.

"If x is A, then y is B" (If x is A, then y is
It can be expressed as the proposition B). here.

"If X is A" is the antecedent part.
).

"y is B" is called a consequent. A and B are "tall" and "old people."

Ambiguous linguistic information such as "a small positive value" can be characterized by the fuzzy membership function as described above. That is, A
, B are fuzzy sets (in the specific circuit description to be described later, A, B, etc. indicate a fuzzy membership function or a voltage distribution representing the fuzzy membership function).

The above proposition can be easily solved x-A-+y■B It is expressed as

Humans often make inferences that include fuzzy expressions in the antecedent and consequent parts. This type of inference cannot be performed satisfactorily using classical pool logic.

Consider the following form of reasoning.

Implication: x
-A → y Tomi B Premise (preo + 1sc): "- membranous modus ponens (generali)
The 0 implication J is also called the major premise, and the premise is also called the minor premise or premise.

There may be multiple implication rules, such as:

Implication 1: x -A -* y -B else or an
d Implication 2: X-A-'y-B else or and Implication r: x-A-by-B.

Premise Knee Conclusion: ymB- Multiple implications are concatenated with else (otherwise) or and (and).

There is also the following form of reasoning.

Implications: X w- A-+y-
B mistake:
ym B - Conclusion
:x-A-This form of reasoning is -membraned modus
They are called modus tollens.

A fuzzy computer basically consists of a fuzzy memory that stores the above-mentioned implication rules,
It consists of a fuzzy inference engine that executes Modus Ponens fuzzy inference.

Let's further analyze the fuzzy reasoning of Modus Ponens.

"Fuzzy relation from A to B"
tionf'rom A to B) Considering the concept of J, this is expressed as RAB (hereinafter simply abbreviated as R).
.

Generally A − (a, a2, −, a , −, a
11 i IllB-f
b, b2,..., b,,..., b 11
When Jn is the fuzzy relation R from A to B, various calculations have been proposed to express this fuzzy relation. For details, see M
asaharu Mizumoto and Hans
-Jurgen Zimmermann, “Comp
arison orFuzzyReasoning M
ethods, Fuzzy Sets and Sys
temsVol, 8. No, 3. pl], 253-
283. (1982).

Typical fuzzy relationships that have already been proposed include the following.

rIj-ajAbj MIN operation rule r
-(a Ab,)■(1-al) MAX rule Ij
I J r,, -1△(1-a, Ab,) Arithmetic rule IJ
I J Since the MIN calculation rule expressed by equation (1) is the most well-known and its effectiveness has been proven in industrial applications, this example uses the calculation rule of equation (1). Adopt. however.

It goes without saying that many other calculation rules are also applicable.

As mentioned above, one implication rule (x
−A −” y −B ), the premise (x=
A'), the conclusion (y −B
``Inference composition rules (compos)'' when inferring
itional rule of 1inference
) J is expressed using the fuzzy relation R as follows.

B--A-*R - [a', a', ..., a,", ..., a]
1 2 1 ff1
- [b', b', ..., b+'
, ..., b °] 1, 2
Jn Various operations have also been proposed for the operation of * in the above equation. For example, one uses M I N/MAX operation, one algebraic product/MAX operation, and so on. In this embodiment, the most commonly used M I N/MAX operation is used as the * operation.

Therefore, the conclusion according to the rules of inferential composition is, is.

*If M I N/MAX operation is used as the operation and equation (1) is used as the fuzzy relationship, it can be expressed as quadratic.

1a, △a, △b, (3)
1 1 J -b, △(M a t△ai) (4) JL,
.

The operations in equation (2), equation (3), or equation (4) are executed by the fuzzy inference engine, which is the main part of the fuzzy computer, in a two-way manner.

From these formulas, the fuzzy inference engine mainly uses MI
It will be understood that it is comprised of an N circuit and a MAX circuit.

Therefore, before describing the configuration of the fuzzy inference engine, the MIN circuit, VAN circuit, and other basic circuits will be explained. Analog electrical signals that indicate the value (grade) of the Menno<-Ship function include voltage signals and current signals.

Below, we will discuss a circuit that operates in voltage mode as an example.

2. MIN circuit, MAX circuit and other basic circuits (1) MIN circuit, MAX circuit n input configured using bipolar transistors -
An example of an output MIN circuit is shown in FIG. 1(A). When the input voltages are Xl, 2 . . . Xn and the output voltage is 2, this circuit performs the calculation Z-/>X. That is, it generates an output voltage equal to the lowest input voltage.

This MIN circuit is composed of a comparator (comparison circuit) and a compensator (compensation circuit). The comparator is composed of n PNP transistors QQ, Q11' 12 13 . x1 to Since the one whose base receives the lowest input voltage (V) becomes conductive, the other transistors become cut-off.Therefore, the emitter has a conductive state due to this input voltage V. In addition, a voltage obtained by adding VEB to the emitter/base voltage of the transistor, that is, V + V, B - Qx, +in ■ appears (VEB is about 0.7 V). If the input voltage is lower than the input voltage, 11
/2 current flows, so the result is the same. The same applies when three or more input voltages are equal and lower than the other input voltages.

The convencator compensates for the voltage VEB appearing as a MIN calculation error in the output of the comparator. This convencator is composed of an NPN (NPN) transistor Q and a transistor Q that serves as a current source to drive current to this transistor Q2. A voltage φ2 necessary for causing a constant current I2 to flow is applied to the base of the transistor Q3. The emitter of transistor Q2 is connected to the output terminal of this MIN circuit. As a result of subtracting the base/emitter voltage vBE of transistor Q2 from the output voltage of the comparator, the output voltage 2 is
It will represent X.

The transistors Q 1 and Q 2 that act as L, l current sources can also be replaced with resistors. Also, the emitter is the power supply VCC
A new PNP (PNP) transistor connected to the transistor Q1 is newly provided, and this transistor and the transistor Q1 form a current mirror. Then, by adjusting the resistor connected in series with the newly installed transistor, the desired current 1
1 can also be made to flow.

FIG. 1(B) shows an improved MIN circuit. Components in this circuit that are the same as those shown in FIG. 1(A) are given the same reference numerals.

In the MIN circuit of FIG. 1(A), transistor Q1
VEB of 1 to Q1n is not necessarily the same value, but considering transistor Q11 as its representative, VEB is
shall be. Let Bj V of transistor Q2 be V. BE by convencator
BE2 The error in the MIN operation is completely compensated for by V,
-V. In other words, BIBE2 − 15 = BIBE2 − 15 = register Q −Q and Q2 are exactly the same “EB
If it has the ll 1n -1 (or VBE-IE) characteristic, the error will be 0 when l-I2. ■ In order to obtain I -1 in the circuit of Figure 1 (A), the voltage ■ φ1. φ2 must be adjusted.

In the improved circuit of FIG. 1(B), a transistor Q4 is provided in series with transistor Q2, and transistor Q2 and transistor Q1 constitute a current mirror.

If a constant current (2) is caused to flow through the transistor Q2, a current (2) corresponding to (1-12) will also flow through the transistor Q1, making it unnecessary to adjust the voltage φ1°I2. Furthermore, if a transistor Q3 as a current source and a transistor Q2 forming a current mirror are provided, and this transistor Q5 is driven by a current source of I2, then 12-Io is always obtained. That is, a constant current C can always flow regardless of fluctuations in the power supply voltages V and V EE, resulting in a circuit that is extremely resistant to fluctuations in the power supply voltage. Also transistor Q6 as a current source for the other MIN circuit. By forming a current mirror with transistor Q5, one current source IO
It becomes possible to drive with

However, this improvement becomes effective when extremely strict calculations are taken into consideration;
As described in the AX circuit, there is no problem in practice even if the currents 11 and 12 are different.

FIG. 2 shows an example of a MAX circuit. This MAX circuit also consists of a comparator and a convencator. The comparator has input voltages X, X, ・
..., base controlled by X 1 2
It consists of NPN transistors Q2□"22'..., Q2n whose emitters are connected to each other, and a transistor Q7 for current driving these transistors.The highest transistor among the transistors Q21 to Q2n Only the transistor to which the input voltage (this is referred to as V) is applied becomes conductive, and a voltage of V V B E appears at the emitter. This -l1
As a result of the error in ax vBE being compensated by a convencator consisting of a PNP transistor Q9 and a transistor Q8 as a current source, there is also a MAX circuit at the output terminal.

It goes without saying that improvements can be made in accordance with the concept shown in FIG. 1(B).

In these MIN circuits and MAX circuits, the input voltage x
1 to Xt represent fuzzy truth values (multivalued membership functions (grade 3). Fuzzy truth values take continuous values [0, 1] from 0 to 1. Corresponding to this, input The voltage is.

For example, it is set to [OV, 5V].

Since all the transistors in the comparators of the MIN circuit and MAX circuit described above are mutually coupled at the emitter, this circuit is named an emitter-coupled fuzzy logic gate (ECFL gate).

The MIN and MAX circuits described above can be thought of as a cascade of two emitter floors driven by current sources (transistors Q 1 , Q 2 , Q 2 , Q8). Therefore, they exhibit very high input impedance and very low output impedance. This fact is.

This shows that these circuits are resistant to external noise and signal crosstalk, which means that many circuits can be connected to subsequent stages.

Further, since the above-mentioned MIN circuit and MAX circuit are driven by a current source, saturation does not occur in each transistor. That is, the accumulation effect of minority carriers in the base region does not occur. therefore.

These circuits exhibit very fast computational speeds. According to experiments, the response speed was 10 nsec or less.

Furthermore, even if one or some of the input terminals of the above-described circuits are opened, the input/output static characteristics of the two circuits as a whole are not affected. This is very important for building large-scale systems.

Furthermore, in the above-described circuit, it is also possible to replace the PNP and NPN transistors with p-channel and n-channel MO3FETs, respectively.

The above applies not only to the MIN circuit and MAX circuit described above, but also to all the circuits described below.

= 19 = (2) Classification of M I N circuits and MAX circuits Next, M I
In addition to considering the developed forms of the N circuit and MAX circuit, for the convenience of explaining the circuits that constitute the fuzzy inference engine, these are classified into several forms.

In the MIN circuit shown in Fig. 1, two inputs X +
In order to consider only X2, transistors Q13 to Q1n for other inputs are omitted. Also input X L I X
2 are respectively set as x+Y. Then, this MIN circuit becomes a 2-man power 1-output MIN circuit that calculates Z-)(Ay.If n such 2-man power 1 output MIN circuits are prepared, as shown in Fig. 3 (A) , 2n input (x
, 2...xn, yl, y2. ...＋V
) n output (zl.

Z2+...,z) becomes a MIN circuit. In this circuit, one output 2 is obtained as Z, -X, Ay by corresponding inputs x1 and yi, and 1 1
1 Do. Therefore, this type of MIN circuit will be referred to as a corresponding MIN circuit (abbreviated as C-MIN). Do the same.

= 20 - z, -x vy, Corresponding M
It is called an AX circuit (abbreviated as C-MAX).

C-MIN and C-MAX are symbolized as shown in FIG. 3(B). Thick arrows similar to bus symbols represent n signal lines. The n written inside this arrow indicates the number of signal lines. Fuzzy O membership function X.

n multi-values of Y are expressed as voltages distributed on each signal line. Therefore, C-MIN.

C-MAX is the MIN of two membership functions X and Y
It can be said that they are circuits for performing calculations and MAX calculations, respectively. Voltages representing n multi-values of the membership function Z generated by the calculation also appear as a distribution on the n signal lines.

In contrast to C-MIN, C-MAX mentioned above.

The n-input 1-output MIN circuit shown in Figures 1 and 2, M
Since the AX circuit outputs the ensemble calculation result of n input signals, it is called an unsampled MIN circuit or an unsampled MAX circuit (abbreviated as E-MIN or E-MAX). These circuits are shown simplified as shown in FIG. 4(A) and symbolized as shown in FIG. 4(B).

Furthermore, we will propose another special MIN circuit.

It is a Cartesian product (or Cartesian product) MIN circuit (Cartesian
sian product MIN circuit:
(abbreviated as CP-MIN). As shown in equation (1), this embodiment employs the MIN operation rule as an operation expressing the fuzzy relationship.

This CP-MIN is.

A-ta, a2. -, a, , -, a
11UA B-fb, b, ..., b, ..., b 1
1 J n as input, the fuzzy relation R-[r, r2.・, r, , −, r col
This is a circuit that outputs Jn rIj-aIAbj.

The symbol of CP-MIN is shown in FIG. 5(A), and a simplified circuit is shown in FIG. 5(B). And the fifth
An example of a circuit symbolized in FIG. 6 as a crossover of lines a, b, and rij is shown in FIG. The circuit of FIG. 6 is a MIN circuit modified to be operated by two people by omitting the transistors Q13 to Qln of the MIN circuit of FIG. In FIG. 6, the same components as those shown in FIG. 1 are given the same reference numerals.

(3) Truncation circuit As shown in Figure 7, the truncation circuit cuts the input membership function X at a certain value a.
The membership function X- obtained as a result of this cutting is output. This circuit is used to build a fuzzy inference engine using MIN, MAX operations, as shown below. The truncation circuit has n inputs, one truncation input a and n outputs.

A specific example of the truncation circuit is shown in FIG. The n inputs representing the fuzzy membership function X are xl, x2 . ..., X, and the traced output fuzzy membership function X' is x',
x “, ..., X °, respectively 12
n It is. This circuit converts the MIN circuit of the two-person car output into n
(i.e., C-MIN), and connect one input of each MIN to each other to perform truncation manually.
It can be said that It can also be said that it is composed of a truncator and a compensator.

(4) MIN-MAX circuit, MAX-MIN circuit MIN
Cascade connection of circuit and MAX circuit.

For the construction of the fuzzy inference engine described later-24
＝ Often used. FIG. 9 shows an example of such a cascade connection. In Figure 9(A), 2m input E-M
The output side of the IN and n-input E-MIN is connected to the input end of a two-person MAX circuit.

Figure 9 (B) shows E-MAX with 1m input and E-MAX with n input.
A circuit is shown in which a two-man power MIN circuit is connected after the MAX. Examples of cascade connection of NIN circuit and MAX circuit are not limited to these, but include C-MIN,:
A cascade connection with E-MAX, a connection between a plurality of parallel E-MINs and E-MAX, etc. are possible.

FIG. 10 shows an embodiment of the circuit shown in FIG. 9(A) using the specific MIN circuit and MAX circuit shown in FIGS. 1(A) and 2. One E-M
The symbols shown in FIG. 1(A) and FIG. 2 are used for the constituent elements of the IN and MAX circuits. However, the transistor Q is given a Ql- symbol. In addition, in the other E-MIN, a dash is added to the symbol of the corresponding element of one E-MIN. Transistor QI
The transistor corresponding to I11 is labeled Q°.

In FIG. 1O, the E-MIN compensator (transistor Q2) compensates for the positive voltage shift at the emitter junction of the preceding comparator, as described above. Further, the convencator (transistor Q9) in the two-power MAX circuit compensates for the negative voltage shift at the emitter junction of the preceding stage comparator. Since the E-MIN compensator and the MAX circuit compensator compensate for voltage shifts in opposite directions, even if these compensators are omitted, the final output 2
There is no change in the value of

A circuit constructed based on this idea by omitting the two-car compensator is shown in FIG.

A comparison with the circuit of FIG. 10 will show that the circuit of FIG. 11 is extremely simplified. This saves transistors, increases operating speed, and reduces power consumption. This convencator abbreviation technique.

Needless to say, it can also be effectively used for cascade connection between a MAX circuit and a MIN circuit or a cascade connection between a truncation circuit and a MAX circuit.

(5) Condroldo MI N-MAX circuit The condrouloid MI N-MAX circuit converts MIN to MAX according to the control input.
circuit or MAX circuit, an example of which is shown in FIG. This circuit has two signal inputs x+y+one control power C and one output 2.

The circuit of FIG. 12 consists of E-MIN transistors Q12 to QIIll in the M I N-MAX circuit of FIG.
.

It is constructed by omitting Q° to Q'. Signal power X+y is applied to the bases of transistors Q and Q', respectively.

Furthermore, an analog switch controlled by control power C is connected between the emitters of transistors Q 2 and Q °. This analog switch consists of a pair of n-channel and p-channel MO8FETs connected in parallel.
Q3. and Q32, and FETQ3□
The control human power C is directly applied to the gate of FET Q32, and the control human power C is inverted by an inverter and applied to the gate of FET Q32.

The control human power C takes binary values, that is, H level (for example, 5V) and L level (for example, OV). When the control human power C is at L level, the analog switch is turned off. In this case, the circuit of FIG.
Since it is the same as the 12 1m 12 In circuit obtained by removing transistors Q-Q and Q' to Q' from the circuit shown in the figure, 2-(△x) V (△y)-
An output of xVy is obtained (△X, △y are equal to x, y,
Although it has no meaning as an arithmetic operation, it works as a >MAX circuit expressed in this way based on the analogy with FIG. 11. When control power C is at H level, the analog switch is turned on and transistors Q and Q' act as comparators, and either transistor Q or Q acts as a compensator, resulting in a MIN circuit (see Figure 1 (A). ). At this time, two current sources Q, Q,'
Therefore, the summed current from both types of current sources Q, Q, and ' flows through the conductive transistor Q and Q'. As a result, the voltage shift at the emitter junction of the conducting transistor is somewhat large, causing a slight error in the compensation by the compensator. However, this error hardly poses a problem in practice. I mean,
This is because the VEB-IE characteristic of the transistor has an extremely steep rise. According to experiments, when the emitter current is 5 mA (7), V EBBO271V, l
At 0IIIA (7), vEB was 0.725V.

Therefore, even if the emitter current IE doubles, only a 0.015V difference will appear in VEB. Assuming that the signal power X or y changes in the range of 0 to 5V (corresponding to the fuzzy truth value of 0 to 1), O,0L5V is a completely negligible value.

3. Fuzzy Inference Engine (1) Basic Inference Engine The fuzzy inference engine, which is a unit that executes the Modus Ponens fuzzy inference mentioned above, will be described.

First, we will explain a basic inference engine that performs a simple inference that includes only one fuzzy proposition (``If X is A: x-AJ'' mentioned above) in the antecedent part of an implication, and then We describe an extended fuzzy inference engine (extended inference engine) that performs inference.

The concept of a basic fuzzy inference engine that performs simple inference is shown in FIG. This inference engine is
Fuzzy membership functions A, B, and A' corresponding to a fuzzy proposition given based on the above-mentioned fuzzy inference composition rules are input, and a fuzzy membership function B' representing a conclusion is output. These fuzzy membership functions A, B, A- and B'' are realized by analog voltages distributed on m or n signal lines corresponding to the elements of the fuzzy set.

The basic fuzzy inference engine is a circuit that executes the calculation of equation (2), equation (3), or equation (4) described above. Since at least three types of fuzzy inference engine configurations are possible corresponding to equations (2), (3), and (4), these are designated as types [lj, [2], and [3].

(2) Type [1] The basic fuzzy inference engine of type [1] is
), and a block diagram thereof is shown in FIG. A voltage input representing a fuzzy membership function A distributed over m signal lines and n
A voltage input representing a fuzzy membership function B distributed on the main signal line is given to CP-MINII, where nXm output voltage signals (r, , j- 1 to n) are obtained. n C-MIN12 are provided, and each C-MIN12
A signal (m
A set of n voltage signals) and a signal r representing the above CP-MIN operation result (r is composed of n voltage j signals) are respectively provided. Each C-MI
The output of N12 is a, m representing △rIj (i-1 to n)
It consists of several voltage signals. Further, n E-MAILs 3 are provided, and each E-MAX 13 performs MAX calculation of m voltage signals inputted thereto. Therefore, a fuzzy membership function B' representing a conclusion as a set of analog voltages distributed over n output signal lines of n E-MAXs 13 can be obtained.

In the cascade connection of C-MIN 12 and E-MAX 13, the compensator can be omitted as described above.

(3) Type [2] The basic fuzzy inference engine of type [2] is
), and a part of its block diagram is shown in FIG. All j (j=1~n
), it is necessary to perform the calculation a1Δa1Δbj (i-1 to m). Therefore, m E-MINs 21 are provided for each value of j, and voltage signals of , ai', a, (im1 to m) are input to each E-M'IN21. A total of nXm E-MINs are required. For each value of j, m outputs of m E-MIN21 are E
- Sent to MAX22. n E-MAX circuits 22 are provided, and each E-MAX 22 outputs a voltage S,'
(j-1 to n) are obtained.

Also in this circuit, the convencator can be omitted in the cascade connection between E-MIN 21 and E-MAX 22.

FIG. 16 shows a specific internal path configuration for obtaining one of the blocks (specifically, b1') in the block diagram shown in FIG. In E-MIN21 and E-MAX22, the same parts as those shown in FIG. 1(^) and FIG. 2 are given the same reference numerals.

Its structure can be easily understood. E-MIN
A multi-output current mirror is constituted by the transistor Q1 which acts as a current source of 21 and the newly provided transistor Q33, and the transistor Q acts as a current source of the current source 1.
1. Therefore, all E-MINs 21 can be driven with the same current with a simple configuration. Similarly, the transistor Q7 as a current source of the E-MAX22 forms a current mirror with the newly provided transistor Q34, and is driven by the current source 1°.

(4) Type [3] The basic fuzzy inference engine of type [3] is
), and its block diagram is shown in FIG. Voltages representing fuzzy fist membership functions A, A-, respectively distributed on n signal lines, are applied to C-MA) 11, where a1°8a
1 (i-1 to m) MIN calculation is performed. That m
These output voltages are input to E-MAX32. This E-M
It is given to the truncation circuit 33 as the AXing power a. On the other hand, the truncation circuit 33 receives voltages (b, , j-1 to kn) representing the fuzzy membership function B distributed on n signal lines. In the end, the truncation circuit 33
Then, the calculation of equation (4) is performed, and a conclusion B' can be obtained as a set of analog voltages b9° distributed on n output lines.

A specific electronic circuit of this type [3] fuzzy inference engine is shown in FIG. In these figures, elements corresponding to those shown in FIG. 1(A), FIG. 2, FIG. 8, and FIG. 16 are given the same reference numerals. C
- A compensator is omitted in the cascade connection of MIN31 and E-MAX32. The truncation circuit 33 is exactly the same as that shown in FIG. C-M
Transistor Q1 as m current sources of IN31 is
Together with the transistor Q■ of the truncation circuit 33.

It constitutes a multi-output current mirror with transistor Q33. Transistor Q7 as a current source in E-MAX32 and transistor Q3 of truncation circuit 33 constitute a multi-output current mirror with transistor Q34.

The type [3] inference engine has a much simpler configuration than the other types [1] and [2] inference engines. The inference engine of this type [3] except for the transistors Q , Q .

It is composed of (4m+5n+1) transistors. Rather than in the form of a monolithic IC.

Experiments using bipolar transistors as discrete components have yielded a calculation speed of 100 ns (IN7 sec). This means that this basic inference engine is 1
This means that it is possible to perform fuzzy inference to, ooo, ooo times per second (10Mega PIPS
: PIPS -Fuzzy Inf'erenee
s Per 5 seconds).

(5) Extended inference engine As shown below, inferences that include two fuzzy propositions in the antecedent part of an implication may be necessary. This is called extended fuzzy inference. The antecedent of an implication is “and/or”
They are joined by J.

Either "and J" or "or J" is selected.

= 36 = Implication: If X is A and/or y is B, then 2 is C (If x Is A andlor y is B
, then z Is C) Blemise: X is A' and/or y is Bo Conclusion = 2 is C-.

This is an implication expressed symbolically as follows: x=A andlor y-B-4-Z-C Error:
Theory: z-C- This extended fuzzy inference is performed by an extended fuzzy inference engine. The concept of an extended inference engine is shown in FIG. The inputs are fuzzy membership functions A, B, C, A= and Bo, and a combination selection C to select the "and/or" combination. The output is a fuzzy membership function C' representing the conclusion.

The phasic membership functions A, A- are due to the voltages distributed on the m signal lines'', and B, B- are due to the voltages distributed on the m'' signal lines.

C is each represented by a voltage distributed on one signal line.

FIG. 20 shows the configuration of this expanded inference engine, which is obtained by slightly modifying the configuration of the basic inference engine of type [3] shown in FIG. 17. Between the fuzzy membership functions A and A″, C−
A MIN calculation is performed (C-MIN 31A), and an E-MAX calculation of m voltages representing the result is performed (E-MAX 32 people). C-MIN and E-MAX calculations are also performed for fuzzy membership functions B and B' (C-MIN31B, E-MAX32B)
. In this example, the combination "and" is realized by a MIN operation, and "or" is realized by a MAX operation. In order to easily perform the operation and selection of this combination, N-MA
An X circuit 34 is used. The two E-MAX calculation results are input to this condord MIN-MAX circuit 34. A combination selection input signal C for selecting "or" from "ka" is provided as a control input to the condolence MIN-MAX circuit 34. The fuzzy membership function C is given to the truncation circuit 33, and the truncation circuit 33 uses the condrol M as its truncation signal.
The output a of the IN-MAX circuit 34 is given. The truncation circuit 33 provides the voltage distribution of the fuzzy membership function representing the conclusion C'.

In the above embodiment, the arithmetic circuits that respectively calculate the combination "and/or" of the fuzzy proposition and the switching circuit that selects the combination arithmetic circuit according to the combination selection input are organically integrated as the Chondral MIN-MAX circuit shown in FIG. The MIN circuit as shown in Figure 1 (A), the MAX circuit as shown in Figure 2, and the input side or output side of these MIN circuit and MAX circuit as a combination selection input. It may also be configured with a circuit that switches accordingly.

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[Brief explanation of the drawing]

FIG. 1(A) is a circuit diagram showing an example of an n-input, one-output NIN circuit, and FIG. 1(B) is a circuit diagram showing an improved type thereof. FIG. 2 is a circuit diagram showing an n-input 1-output MAX circuit. Figures 3 to 6 show the classification of MIN circuits or MAX circuits, and Figure 3 (A) shows the corresponding MI circuit.
N (C-MIN) or correspondent MAX
(C-MAX), Figure 3 (B) shows its symbols, and Figure 4 (A) shows the unsample MIN (E
-MIN) or ensample MAX (E-MAX)
Figure 4 (B) shows the concept of
P-MIN), FIG. 5(B) shows a simplified circuit thereof, and FIG. 6 shows a specific example of the circuit symbolized as a line crossing in FIG. 5(B). It is a diagram. FIG. 7 shows the concept of a truncation circuit. FIG. 8 is a schematic diagram showing a specific example of the truncation circuit. 9(A) and 9(B) are block diagrams showing the cascade connection of the NIN circuit and MAX circuit, respectively. FIG. 10 is a circuit diagram showing a specific example of the circuit in FIG. 9(A). FIG. FIG. 11 is a circuit diagram showing a circuit of FIG. 10 with the convencator omitted; FIG. 12 is a circuit diagram showing a condodrome M I N-MAX circuit. FIG. 13 shows the concept of a basic fuzzy inference engine. FIG. 14 is a block diagram showing the configuration of a type [1] fuzzy inference engine. FIG. 15 is a block diagram showing part of the configuration of a type [2] fuzzy inference engine, and FIG. 16 is a circuit diagram showing its specific circuit. FIG. 17 is a block diagram showing the configuration of a type [3] fuzzy inference engine, and FIG. 18 is a circuit diagram showing its specific circuit. FIG. 19 shows the concept of an extended fuzzy inference engine, and FIG. 20 is a block diagram showing an example of its configuration. QQ: FET for coupling switching. 31° 32 C...Connection selection input. Patent applicant Tateishi Electric Co., Ltd. Agent Patent attorney Kenji Ushiku (and 1 other person) 3rd (A) (B) 4th (A) -147・CB) ・Kinban C5'71 〉 12ε≦ ! +1 i i B' Figure 19 Figure 20 A'AB'BC

Claims (1)

[Claims] In a fuzzy inference engine that executes a modus ponens that includes an implication having two fuzzy propositions in its antecedent part, an arithmetic circuit that operates on the combination and/or of two fuzzy propositions, and a combination selection. A fuzzy inference engine equipped with a switching circuit that selects a combination arithmetic circuit according to input.