JPS63122394U - - Google Patents
Info
- Publication number
- JPS63122394U JPS63122394U JP1987014698U JP1469887U JPS63122394U JP S63122394 U JPS63122394 U JP S63122394U JP 1987014698 U JP1987014698 U JP 1987014698U JP 1469887 U JP1469887 U JP 1469887U JP S63122394 U JPS63122394 U JP S63122394U
- Authority
- JP
- Japan
- Prior art keywords
- cursor
- shape
- register
- storing
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Digital Computer Display Output (AREA)
Description
第１図は本考案の一実施例を示すカーソルメモ
リ制御回路のブロツク図、第２図は本考案の一実
施例におけるカーソルメモリに記憶されるカーソ
ル形状を示す図、第３図はカーソルメモリ制御回
路を備えたビツトマツプデイスプレイ制御回路の
ブロツク図、第４図は従来のカーソルメモリ制御
回路を示す図、第５図はタイミング波形を示す図
、第６図はカーソル形状を示す図である。
１……ＣＲＴコントローラ、２……ビデオメモ
リ、３１，３２……シフトレジスタ、４……カー
ソルメモリ制御回路、５，６，７……カウンタ、
８……カーソルメモリ、９……レジスタ。
Fig. 1 is a block diagram of a cursor memory control circuit showing an embodiment of the present invention, Fig. 2 is a diagram showing a cursor shape stored in the cursor memory in an embodiment of the present invention, and Fig. 3 is a cursor memory control circuit. 4 is a diagram showing a conventional cursor memory control circuit, FIG. 5 is a diagram showing timing waveforms, and FIG. 6 is a diagram showing a cursor shape. 1... CRT controller, 2... Video memory, 31, 32... Shift register, 4... Cursor memory control circuit, 5, 6, 7... Counter,
8...Cursor memory, 9...Register.
Claims (1)
イスプレイにおいて、カーソル形状を記憶するた
めの複数のブロツクに分割されたカーソルメモリ
と、複数のブロツクのうちどのブロツクに記憶さ
れたカーソル形状を表示するか指定するデータを
格納するレジスタを備え、該レジスタの出力デー
タをカーソルメモリの上位アドレスとすることを
特徴とするビツトマツプデイスプレイのカーソル
制御装置。 In a bitmap display that displays a cursor of arbitrary shape, the cursor memory is divided into multiple blocks for storing the cursor shape, and data that specifies which of the multiple blocks the cursor shape stored in is to be displayed. 1. A cursor control device for a bitmap display, comprising a register for storing a cursor, and output data of the register is used as an upper address of a cursor memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987014698U JPS63122394U (en) | 1987-02-03 | 1987-02-03 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987014698U JPS63122394U (en) | 1987-02-03 | 1987-02-03 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63122394U true JPS63122394U (en) | 1988-08-09 |
Family
ID=30804925
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987014698U Pending JPS63122394U (en) | 1987-02-03 | 1987-02-03 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63122394U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59125783A (en) * | 1982-12-31 | 1984-07-20 | 富士通株式会社 | Display unit |
-
1987
- 1987-02-03 JP JP1987014698U patent/JPS63122394U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59125783A (en) * | 1982-12-31 | 1984-07-20 | 富士通株式会社 | Display unit |
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