JPS63120532A - Automatic gain control circuit - Google Patents
Automatic gain control circuitInfo
- Publication number
- JPS63120532A JPS63120532A JP26616686A JP26616686A JPS63120532A JP S63120532 A JPS63120532 A JP S63120532A JP 26616686 A JP26616686 A JP 26616686A JP 26616686 A JP26616686 A JP 26616686A JP S63120532 A JPS63120532 A JP S63120532A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- output
- amplitude
- maximum value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- 230000003321 amplification Effects 0.000 claims description 4
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 4
- 238000005070 sampling Methods 0.000 abstract description 9
- 238000010586 diagram Methods 0.000 description 12
- 239000003990 capacitor Substances 0.000 description 9
- 230000000694 effects Effects 0.000 description 5
- 101000802471 Sylvirana guentheri Brevinin-2GHb Proteins 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 238000005562 fading Methods 0.000 description 3
- UXFQFBNBSPQBJW-UHFFFAOYSA-N 2-amino-2-methylpropane-1,3-diol Chemical compound OCC(N)(C)CO UXFQFBNBSPQBJW-UHFFFAOYSA-N 0.000 description 1
- 101000802478 Sylvirana guentheri Brevinin-2GHa Proteins 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- CQTRUFMMCCOKTA-UHFFFAOYSA-N diacetoneamine hydrogen oxalate Natural products CC(=O)CC(C)(C)N CQTRUFMMCCOKTA-UHFFFAOYSA-N 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
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Abstract
Description
【発明の詳細な説明】
（概要〕
多値ＱＡＭ或いはＳＳＢ変調のマイクロ波信号などの受
信回路に用いられるＡＧＣ回路であって、入力する受信
搬送波信号の振幅の一定時間内の最大値を記憶するピー
クホールド回路と、その記憶した最大値をサンプルして
次の最大値までホールドするサンプルホールド回路をＩ
ｉえて、高速のマイクロ波信号の振幅成分に歪を与える
ことなく、しかもフェージングなどの信号入力の変動に
対して良好な振幅制御動作を行うＡＧＣ回路。[Detailed Description of the Invention] (Summary) An AGC circuit used in a receiving circuit for multi-level QAM or SSB modulated microwave signals, etc., which stores the maximum value of the amplitude of an input received carrier signal within a certain period of time. I have a peak hold circuit and a sample hold circuit that samples the stored maximum value and holds it until the next maximum value.
In addition, an AGC circuit that does not distort the amplitude component of a high-speed microwave signal and performs a good amplitude control operation against fluctuations in signal input such as fading.
本発明は多値ＨＡＭ （直交振幅変調）やＳＳＢ変調
のマイクロ波信号など、信号振幅に伝送情報を含む高速
の搬送波入力信号を可変利得増幅器で増幅して出力搬送
波のレベルを一定値になるように前記増幅器の利得を自
動制御する自動利得制御（ＡＧＣ）回路に関する。The present invention amplifies a high-speed carrier wave input signal containing transmission information in the signal amplitude, such as a multilevel HAM (quadrature amplitude modulation) or SSB modulated microwave signal, with a variable gain amplifier so that the level of the output carrier wave becomes a constant value. The present invention relates to an automatic gain control (AGC) circuit that automatically controls the gain of the amplifier.
多値ＱＡＭ信号波はｎ値の振幅値を有する高速ディジタ
ル信号であるので、多値ＱＡＭ信号波のＡＧＣ回路とし
ては、応答の時定数が小さく高速で応答して入力搬送波
信号のフェージングなどによる変動に対して一定レベル
の搬送波信号を出力すると同時に信号の振幅成分に歪を
与えることの無いことが望まれている。Since the multi-level QAM signal wave is a high-speed digital signal with an amplitude value of n values, the AGC circuit for the multi-level QAM signal wave has a small response time constant and responds at high speed to avoid fluctuations due to fading of the input carrier signal. It is desired to output a carrier wave signal at a constant level without causing distortion to the amplitude component of the signal.
従来のＡＧＣ回路は、第５図のブロック図に示すごとく
、入力搬送波信号Ｅｉｎを可変利得増幅器ＡＧＣＡＭＰ
により増幅して出力搬送波信号Ｅｏｕ ｔを出力する回
路において、出力搬送波信号Ｅ ｏｕｔの一部を時定数
回路ＣＲをもつ検波器ＤＥＴにより検波し、検波器ＯＵ
Ｔの直流検波出力を直流増幅器ＤＣＡＷＰで増幅して前
記可変利得増幅器ＡＧＣＡ？ＩＰに加え可変利得増幅器
ＡＧＣＡＭＰの増幅利得を制御して搬送波出力［！ｏｕ
ｔの振幅を一定にする構成になっている。As shown in the block diagram of FIG. 5, the conventional AGC circuit converts the input carrier signal Ein into a variable gain amplifier AGCAMP.
In a circuit that outputs an output carrier signal Eout by amplifying the output carrier signal Eout, a part of the output carrier signal Eout is detected by a detector DET having a time constant circuit CR, and a part of the output carrier signal Eout is detected by a detector DET having a time constant circuit CR.
The DC detection output of T is amplified by the DC amplifier DCAWP and the variable gain amplifier AGCA? In addition to IP, the amplification gain of the variable gain amplifier AGCAMP is controlled to output the carrier wave [! ou
The configuration is such that the amplitude of t is kept constant.
第５図の従来のＡＧＣ回路を、真速の多値ＱＡＭマイク
ロ波信号波の受信機などに使用すると、多値ＱＡＭマイ
クロ波信号は伝送情報を振幅と位相の両方により伝送す
るものであるため、伝送される搬送波信号は、振幅値が
一定ではなく変調信号により変化する信号である。When the conventional AGC circuit shown in Fig. 5 is used in a receiver of a true-speed multi-level QAM microwave signal wave, it is difficult to use the multi-level QAM microwave signal because the multi-level QAM microwave signal transmits transmission information using both amplitude and phase. , the transmitted carrier wave signal is a signal whose amplitude value is not constant but changes depending on the modulation signal.
それで、高速の多値ＱＡＭの搬送波信号に応答するため
ＡＧＣ回路の検波器ＤＥＴの時定数ＣＲを小さい値に選
ぶと、ＡＧＣ動作の応答が速くなってＡＧＣ回路の制御
信号が多値［ＩＡＭ信号の振幅変化に追随してしまい、
受信搬送波信号の振幅に歪を生ずる。Therefore, if the time constant CR of the detector DET of the AGC circuit is selected to be a small value in order to respond to a high-speed multi-value QAM carrier signal, the response of the AGC operation becomes faster and the control signal of the AGC circuit changes to a multi-value [IAM signal]. It follows the amplitude change of
This causes distortion in the amplitude of the received carrier signal.
従って、検波器ＤＥＴの時定数ＣＲの値は、伝送信月の
１タイムスロツトの約１０ 倍以上としなければなら
ない。Therefore, the value of the time constant CR of the detector DET must be approximately 10 times or more the time slot of one transmission month.
時定数ＣＲをこのような大きな値にすると、こんどは、
高速の多値ＱＡＭ信号入力波にＡＧＣ回路の制御動作が
追従出来ないという問題が生じる。When the time constant CR is set to such a large value,
A problem arises in that the control operation of the AGC circuit cannot follow the high-speed multi-level QAM signal input wave.
上記の従来のＡＧＣ回路の問題点は、第１図の原理ブロ
ック図に示すごとく、可変利得増幅器３の出力搬送波Ｅ
ｏｕ ｔの振幅値の一定時間における最大値を検出して
記憶するピークボールド回路１と、該ピークボールド回
路ｌの直流出力を前記一定時間毎にサンプルしてそのサ
ンプル値を次の最大値がサンプルされて到達するまで保
持するサンプルホールド回路２を設け、該サンプルホー
ルド回路２の保持した直流出力を制御信号として可変利
得増幅器３に加え、その増幅利得を自動制御するように
構成する本発明によって解決される。The problem with the above-mentioned conventional AGC circuit is that, as shown in the principle block diagram of FIG.
a peak bold circuit 1 that detects and stores the maximum value of the amplitude value of out t in a certain period of time; and a peak bold circuit 1 that samples the DC output of the peak bold circuit 1 at the specified period of time and uses the sampled value as the sample for the next maximum value. This problem is solved by the present invention, in which a sample-and-hold circuit 2 is provided to hold the sample-and-hold circuit 2 until the sample and hold circuit 2 reaches the target, and the DC output held by the sample-and-hold circuit 2 is applied as a control signal to the variable gain amplifier 3, so that the amplification gain is automatically controlled. be done.
本発明のピークホールド回路１は、可変利得増幅器３の
出力搬送波Ｅｏｕ ｔの振幅の数十〜数百タイムスロッ
トの一定時間内における最大値を検出して記憶し、サン
プルボールド回路２は前記ピークホールド回路１の出力
を同じ数十〜数百タイムスロットの一定時間間隔でサン
プルして、ピークホールド回路１が記憶した信号振幅の
最大値を次のサンプルの最大値が来るまで保持するので
、サンプルボールド回路２の直流出力を制御信号として
可変利得増幅器３に加えると、可変利得増幅器３の利得
は、多値ＱＡＭ信号波のタイムスロット毎の個々の信号
振幅の変化には追随せず、数十〜数百タイムスロット毎
の信号振幅の最大値のみに追従する。The peak hold circuit 1 of the present invention detects and stores the maximum value of the amplitude of the output carrier wave Eout of the variable gain amplifier 3 within a certain period of several tens to hundreds of time slots, and the sample bold circuit 2 detects and stores the maximum value of the amplitude of the output carrier wave Eout of the variable gain amplifier 3. The output of circuit 1 is sampled at fixed time intervals of the same tens to hundreds of time slots, and the maximum value of the signal amplitude stored in peak hold circuit 1 is held until the maximum value of the next sample arrives. When the DC output of the circuit 2 is applied as a control signal to the variable gain amplifier 3, the gain of the variable gain amplifier 3 does not follow the changes in the individual signal amplitudes for each time slot of the multilevel QAM signal wave, but is in the range of several tens to Tracks only the maximum signal amplitude every several hundred time slots.
したがって、可変利得増幅器３のＡＧＣ動作は高速の多
値ＱＡＭ信号波に対して一定レベルの搬送波信号を出力
する満足なＡＧＣ動作を行い、かつ、高速の受信搬送波
信号の振幅成分に歪を与えるというようなことはなくな
って問題が無くなる。Therefore, the AGC operation of the variable gain amplifier 3 performs a satisfactory AGC operation that outputs a constant level carrier signal for a high-speed multilevel QAM signal wave, and also distorts the amplitude component of the high-speed received carrier signal. This will no longer be the case and the problem will disappear.
第２図は本発明の実施例の自動利得制御回路の構成を示
すブロック図で、第３図は本実施例の動作を説明するた
めの波形図、第４図は本実施例の自動利得制御回路のピ
ークホールド回路（図へ）およびサンプルホールド回路
（図Ｂ）の回路図を示す。FIG. 2 is a block diagram showing the configuration of an automatic gain control circuit according to an embodiment of the present invention, FIG. 3 is a waveform diagram for explaining the operation of this embodiment, and FIG. 4 is an automatic gain control circuit according to an embodiment of the present invention. The circuit diagrams of the peak hold circuit (Figure B) and sample hold circuit (Figure B) of the circuit are shown.
第２図の可変利得増幅器３の出力搬送波信号Ｅｏｕｔの
一部は、ピークホールド回路１のピーク検波器１１のダ
イオードで検波され、出力搬送波Ｅｏｕ ｔの振幅最大
値に等しい検波直流電圧が抵抗Ｒの両端に得られる。こ
のピーク検波器１１の検波直流出力は電圧ホールド回路
１２の演算増幅器０１’ ＡＭＰＯ＋入力端子に入力さ
れる。A part of the output carrier wave signal Eout of the variable gain amplifier 3 in FIG. You get it on both ends. The detected DC output of the peak detector 11 is input to the operational amplifier 01' AMPO+ input terminal of the voltage hold circuit 12.
演算増幅器Ｏｒ’ ＡＭＰの出力は自分の一入力端子に
接続されると同時に、コンデンサＣ１を充電する。The output of the operational amplifier Or' AMP is connected to its one input terminal and simultaneously charges the capacitor C1.
コンデンサＣ１は、演算増幅器ＯＰ ＡＭＰの出力の直
流出力により次々と充電されその最大値を保持するが、
コンデンサＣＩの両端に接続されたりセットスイッチＳ
Ｗｏにより、一定時間毎にリセットされる。The capacitor C1 is charged one after another by the DC output of the operational amplifier OP AMP and maintains its maximum value.
Connected to both ends of capacitor CI or set switch S
It is reset by Wo at regular intervals.
このコンデンサＣＩのり七ソト動作は、第３図へに示す
如く、ピークボールド回路への一定時間毎の制御信号、
すなわち、数十〜数百タイムスロットの時間毎のりセン
トパルスによって行われるので、コンデンサＣ１の充電
電圧は、数十〜数百タイムスロットにおける搬送波信号
出力Ｅｏｕｔの最大値を示すことになる。This operation of the capacitor CI is performed by sending a control signal to the peak bold circuit at regular intervals, as shown in FIG.
That is, since charging is performed by cent pulses every time in several tens to hundreds of time slots, the charging voltage of the capacitor C1 indicates the maximum value of the carrier wave signal output Eout in several tens to several hundred time slots.
このコンデンサＣ１の充電電圧、すなわち、ピークボー
ルド回路１の出力電圧Ｖｏｕｔ １は、次のサンプルホ
ールド回路２のサンプリング回路２１の演算増幅器ＡＭ
Ｐ−１の十入力端子に入力され、そのＡＦＩＰ−１の出
力がサンプリング用のオン・スイッチ５Ｗ−１を介して
電圧ホールド回路２２のコンデンサＣ２を充電する。Ａ
ＭＰ−１の出力は、また、電圧ホールド回路２２の演算
増幅器ＡＭＰ−２の十入力端子に入力される。The charging voltage of this capacitor C1, that is, the output voltage Vout 1 of the peak bold circuit 1 is the operational amplifier AM of the sampling circuit 21 of the next sample hold circuit 2.
The output of AFIP-1 charges the capacitor C2 of the voltage hold circuit 22 via the sampling on switch 5W-1. A
The output of MP-1 is also input to the ten input terminal of the operational amplifier AMP-2 of the voltage hold circuit 22.
演算増幅器ＡＭＰ−２の出力電圧Ｖｏｕｔ ２は自分の
一入力端子に接続されると同時に、サンプリング回路２
１の抵抗Ｒ１と抵抗Ｒ２の直列抵抗回路を介して演算増
幅器ＡＭＰ−１の一入力端子に入力される。The output voltage Vout 2 of the operational amplifier AMP-2 is connected to its own one input terminal, and at the same time, the output voltage Vout 2 of the operational amplifier AMP-2 is connected to its own input terminal.
The signal is input to one input terminal of the operational amplifier AMP-1 through a series resistance circuit including one resistor R1 and one resistor R2.
また、直列抵抗回路の抵抗Ｒ１とＲ２の接続点は、サン
プリンゲス用のオフ・スイッチ５Ｗ−２を介してオン・
スイッチ舖−１の入力側に接続される。 サンプリンゲ
ス用のオン・スイッチ５Ｗ−１とオフ・スイッチ５Ｗ−
２は、第４図Ｂに示す如きサンプルホールド回路制御の
サンプリングパルスによって駆動されるが、サンプリン
グパルスの周期は前記ピークホールド回路のリセットパ
ルスの周期と同じで、ピークホールド回路１の出力電圧
Ｖｏｕｔ １が、数十〜数百タイムスロットの一定時間
毎にサンプリングされてコンデンサＣ２を充電し直流電
圧として保持される。Furthermore, the connection point between the resistors R1 and R2 of the series resistance circuit is turned on and off via the off switch 5W-2 for sampling.
Connected to the input side of switch 1. On switch 5W-1 and off switch 5W- for sampling
2 is driven by a sampling pulse controlled by a sample hold circuit as shown in FIG. is sampled at fixed intervals of several tens to hundreds of time slots, charges the capacitor C2, and is held as a DC voltage.
コンデンサＣ２に保持された直流電圧は、演ｑ４増幅器
ＡにＰ−２の出力端より直流出力Ｖｏｕｔ ２として出
力され、可変利得増幅器３にＡＧＣの制御信号として加
えられ増幅器３の利得を制御してへＧＣ動作を行う。The DC voltage held in the capacitor C2 is outputted from the output terminal of P-2 to the q4 amplifier A as a DC output Vout 2, and is applied to the variable gain amplifier 3 as an AGC control signal to control the gain of the amplifier 3. Performs GC operation.
本実施例のＡＧＣ回路の可変利得増幅器３の制御信号Ｖ
ｏｕｔ２は、ＡＧＣ回路の出力搬送波信号Ｅｏｕｔの振
幅の数十〜数百タイムスロット間における最大値である
直流電圧Ｖｏｕｔ １を、同じ周期の数十〜数百タイム
スロットの一定時間毎にサンプリングしたサンプル値な
ので、本実施例のＡＧＣ回路の制御信号となる直流出力
Ｖｏｕ ｔ２は、従来のＡＧＣ回路と比較して応答時間
が１／１００以下の高速の応答が得られ、フェージング
などによる入力信号レベルの変化に追従して満足なＡＧ
Ｃ動作をする。一方、制御信号Ｖｏｕ ｔ２は入力搬送
波信号Ｅｉｎのタイムスロット毎の個々の振幅変化には
追従しないので、多値０ΔＨ信号波などの振幅成分に歪
を与えることはなく、高速の多値ＱＡＭやＳＳＢ変調の
マイクロ波信号のＡＧＣ回路として従来例におけるよう
な振幅歪の問題は無い。Control signal V of the variable gain amplifier 3 of the AGC circuit of this embodiment
out2 is a sample obtained by sampling the DC voltage Vout1, which is the maximum amplitude of the output carrier signal Eout of the AGC circuit between tens to hundreds of time slots, at regular intervals of several tens to hundreds of time slots with the same period. Therefore, the DC output Vout2, which is the control signal of the AGC circuit of this embodiment, has a high-speed response with a response time of 1/100 or less compared to the conventional AGC circuit, and the input signal level does not change due to fading etc. Satisfied AG by following changes
Perform C action. On the other hand, since the control signal Vout2 does not follow the individual amplitude changes for each time slot of the input carrier signal Ein, it does not distort the amplitude components such as multi-value 0ΔH signal waves, and is suitable for high-speed multi-value QAM and SSB. As an AGC circuit for a modulated microwave signal, there is no problem of amplitude distortion as in the conventional example.
以上説明した如く、本発明によれば、従来のＡＧＣ回路
の１／１００以下の応答時間で入力レベル変動に高速応
答できて、かつ、多値ＱＡＭやＳＳＢ変調のマイクロ波
信号の振幅成分に悪い影響を与えない良好な自動利得制
御回路が得られる効果がある。As explained above, according to the present invention, it is possible to quickly respond to input level fluctuations with a response time of 1/100 or less of the conventional AGC circuit, and it is possible to quickly respond to input level fluctuations with a response time of 1/100 or less of a conventional AGC circuit. This has the effect of providing a good automatic gain control circuit that does not have any adverse effects.
また、ＳＳＢ変調信号波のＡＧＣ回路として使用する場
合には、従来例において必要としていたパイロット信号
の挿入、分岐回路が不要となり、回路の簡素化に役立つ
効果も得られる。Furthermore, when used as an AGC circuit for SSB modulated signal waves, the pilot signal insertion and branching circuits required in the conventional example are no longer necessary, and the effect of simplifying the circuit can be obtained.
第１図は本発明の自動利得制御回路の構成を示す原理ブ
ロック図、
第２図は本発明の実施例の自動利得制御回路の構成を示
すブロック図、
第３図は本発明の実施例の自動利得制御回路の動作を説
明するための波形図、
第４図は本発明の実施例の自動利得制御回路のピークボ
ールド回路とサンプルホールド回路の回路図、
第５図は従来例の自動利得制御回路の構成を示すブロッ
ク図である。
第１図、第２図において、
１はピークホールド回路、
１１はピーク検波器、１２は電圧ホールド回路、２はサ
ンプルホールド回路、
２１はサンプリング回路、２２は電圧ホールド回路であ
る。
早 １ 口FIG. 1 is a principle block diagram showing the configuration of an automatic gain control circuit according to the present invention, FIG. 2 is a block diagram showing the configuration of an automatic gain control circuit according to an embodiment of the present invention, and FIG. 3 is a block diagram showing the configuration of an automatic gain control circuit according to an embodiment of the present invention. A waveform diagram for explaining the operation of the automatic gain control circuit, Fig. 4 is a circuit diagram of the peak bold circuit and sample hold circuit of the automatic gain control circuit according to the embodiment of the present invention, and Fig. 5 is a circuit diagram of the automatic gain control circuit of the conventional example. FIG. 2 is a block diagram showing the configuration of a circuit. 1 and 2, 1 is a peak hold circuit, 11 is a peak detector, 12 is a voltage hold circuit, 2 is a sample hold circuit, 21 is a sampling circuit, and 22 is a voltage hold circuit. 1 sip early
Claims (1)
幅利得可変の増幅器（３）と、前記増幅器（３）の出力
搬送波信号の振幅値の一定時間における最大値を記憶し
て出力するピークホールド回路（１）と、該ピークホー
ルド回路（１）の出力を前記一定時間毎にサンプルして
保持するサンプルホールド回路（２）から成り、該サン
プルホールド回路（２）の出力を制御信号として前記増
幅器（３）の増幅利得を自動制御するようにしたことを
特徴とする自動利得制御回路。An amplifier (3) with variable amplification gain that amplifies an input carrier signal and outputs an output carrier signal, and a peak hold circuit that stores and outputs the maximum value of the amplitude value of the output carrier signal of the amplifier (3) over a certain period of time. (1), and a sample-hold circuit (2) that samples and holds the output of the peak-hold circuit (1) at fixed time intervals, and uses the output of the sample-hold circuit (2) as a control signal to control the amplifier ( 3) An automatic gain control circuit characterized in that the amplification gain is automatically controlled.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26616686A JPS63120532A (en) | 1986-11-07 | 1986-11-07 | Automatic gain control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26616686A JPS63120532A (en) | 1986-11-07 | 1986-11-07 | Automatic gain control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63120532A true JPS63120532A (en) | 1988-05-24 |
| JPH0564893B2 JPH0564893B2 (en) | 1993-09-16 |
Family
ID=17427190
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26616686A Granted JPS63120532A (en) | 1986-11-07 | 1986-11-07 | Automatic gain control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63120532A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5203016A (en) * | 1990-06-28 | 1993-04-13 | Harris Corporation | Signal quality-dependent adaptive recursive integrator |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57181236A (en) * | 1981-04-30 | 1982-11-08 | Fujitsu Ltd | Waveform amplification detecting system |
-
1986
- 1986-11-07 JP JP26616686A patent/JPS63120532A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57181236A (en) * | 1981-04-30 | 1982-11-08 | Fujitsu Ltd | Waveform amplification detecting system |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5203016A (en) * | 1990-06-28 | 1993-04-13 | Harris Corporation | Signal quality-dependent adaptive recursive integrator |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0564893B2 (en) | 1993-09-16 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |