JPS63119258U - - Google Patents
Info
- Publication number
- JPS63119258U JPS63119258U JP1104287U JP1104287U JPS63119258U JP S63119258 U JPS63119258 U JP S63119258U JP 1104287 U JP1104287 U JP 1104287U JP 1104287 U JP1104287 U JP 1104287U JP S63119258 U JPS63119258 U JP S63119258U
- Authority
- JP
- Japan
- Prior art keywords
- chip
- bonding pad
- wire bonding
- base
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Fuses (AREA)
- Bipolar Transistors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1104287U JPS63119258U (de) | 1987-01-27 | 1987-01-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1104287U JPS63119258U (de) | 1987-01-27 | 1987-01-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63119258U true JPS63119258U (de) | 1988-08-02 |
Family
ID=30797901
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1104287U Pending JPS63119258U (de) | 1987-01-27 | 1987-01-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63119258U (de) |
-
1987
- 1987-01-27 JP JP1104287U patent/JPS63119258U/ja active Pending