JPS6311820B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device that converts various types of data into binary codes and transmits and processes them bit by bit and word by word. It relates to a transmitting/receiving device.

In a device that converts data into binary code and sequentially transmits it bit by bit and word by word,
A bit synchronization signal and a word synchronization signal are required when decoding received data.

Therefore, as a device for bit synchronization signals,
Devices that provide a bit signal generation circuit on the receiving side and perform synchronization using the code conversion point of received data, and devices that transmit a bit synchronization signal along with the data and reproduce it on the receiving side have been proposed and put into practical use. In addition, as a device for word synchronization signals, the receiving side detects the state of a special code in the received data, such as a state in which 10 or more bits of logical value "1" or "0" are consecutive. A device for synchronizing created word synchronization signals is in practical use.

However, in conventional devices, there is no relationship between the bit synchronization signal and the word synchronization signal, so in order to synchronize both synchronization signals, a synchronization signal generation circuit,
A plurality of complicated and expensive circuits such as a synchronization detection circuit must be provided, which not only increases the cost but also increases the number of circuit elements, making the device that much more complicated.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transmitting/receiving device that can transmit only one type of synchronization signal and generate both a bit synchronization signal and a word synchronization signal on the receiving side with a simple and inexpensive circuit. .

According to the present invention, the above object is achieved by sequentially shifting the phase by a predetermined angle each time one bit of data is transmitted, and from leading phase to lagging phase and from lagging phase to leading phase each time one word of data is transmitted. A transmitter side is provided with a synchronization signal generating circuit of a constant frequency controlled by the phase and a means for adding and outputting this synchronization signal and data to be transmitted, and a change in the phase of the synchronization signal in the input signal is detected. This is achieved by providing a circuit on the receiver side for detecting and creating a bit synchronization signal and a word synchronization signal.

In this way, the synchronization signal generation circuit on the transmitter side and the synchronization signal generation circuit on the receiver side can be configured by combining circuits made of commercially available ICs, so mutually related bit synchronization can be performed. Both the signal and the word synchronization signal can be obtained with a simple and inexpensive circuit.

The present invention will be described below based on embodiments shown in the drawings.

In FIG. 1, A is a transmitter and B is a receiver. Transmitter A includes a transmission data conversion circuit 1 that converts data to be transmitted into a modulated wave signal and outputs the same, and a synchronization signal of a constant frequency whose phase is shifted by a predetermined angle for each bit of data to be transmitted. It includes a generation circuit 2 and an addition circuit 3 that superimposes the modulated wave signal and a synchronization signal and outputs the resultant to the receiver B.
Receiver B includes a synchronization signal generation circuit 4 that creates a bit synchronization signal and a word synchronization signal using the received synchronization signal, and a regeneration circuit 5 that reproduces received data using both synchronization signals.

The transmission data conversion circuit 1 includes a clock signal CP generating circuit ₁ having a constant frequency F1 as shown in FIG. 2A.
0, a bit counter 11 that counts the clock signal, a data selector circuit 14 that outputs bit information corresponding to the counted value of the bit counter 11 among the data to be transmitted inputted from the data output circuit 12, and this circuit. A modulation circuit 15 that modulates the carrier wave signal using the output signal of 13 is provided.

The bit counter 11 is a known binary counter that counts the clock signal and outputs the count value in binary code, and the count value is the same number as the number of bits of data for one word (for example, 8 or 16 bits). When this happens, it is cleared and counted repeatedly.

The data output circuit 12 is a buffer circuit that temporarily stores data to be transmitted output from a central processing unit using an electronic computer, and is composed of the same number of bits as the number of bits of one word of data. Each bit of this circuit 12 is set with the next word of data each time the transmission of one word of data is completed.

The data selector circuit 13 is the data output circuit 1
2, the information of the bit specified by the count value of the bit counter 11 is the logical value "H".
This is a known circuit that outputs a signal of a level depending on whether the bit counter 1 is
1 is 1, 2, 3......X, 1, 2......(However,
(X is the number of bits of data for one word, that is, the same number as the number of bits of the data output circuit), the signal of the level corresponding to the information of each bit of the data output circuit 12 is set to the first bit, 2nd bit.......Sequentially and repeatedly output in the order of the Xth bit.

As such a data selector circuit, a commercially available IC selector circuit (for example, model number SN74150) can be used. In this case, the data input terminals may be individually connected to the output terminals of each bit of the data output circuit 12, and the input terminals for the data designation signal may be individually connected to the output terminals of each bit of the bit counter 11.

The modulation circuit 14 modulates the carrier signal of constant frequency F ₂ with the output signal of the data selector circuit 13 and amplifies the modulated carrier signal, and then modulates the carrier signal with the output signal of the data selector circuit 13 .
This is a known circuit that outputs This modulation circuit 14
The modulation method can be a known modulation method such as frequency modulation, phase modulation, amplitude modulation, frequency displacement modulation, or phase displacement modulation.

The synchronization signal generation circuit 2 is a synchronization signal generation circuit whose phase differs for each bit of data to be transmitted and is switched between an advanced phase and a delayed phase for each word. In this example, the synchronization signal frequency f is 4.
Generation circuit 20 of reference square wave signal 4f with double frequency
and four types of rectangular wave signals fψ ₀ , fψ ₁ , fψ ₂ , with frequencies f whose phases are sequentially shifted by 90 degrees using the above rectangular wave signals.
fψ ₃ , a trigger type flip-flop 22 that is triggered every time the count value of the bit counter 11 becomes "0", and the output signal of the flip-flop 22 is input as an up/down control signal, and a clock A 2-bit up/down counter 2 to which the output signal CP of the signal generation circuit 10 is input to the clock signal input terminal.
3, a selector circuit 24 that selects and outputs one of the output signals of the conversion circuit 21 using the output signal of the flip-flop 23, and a band filter 25 that passes the frequency f component in the output signal of the selector circuit 24. It is equipped with

In this example, the conversion circuit 21 is composed of four frequency division phase shift circuits 21 ₀ , 21 ₁ , 21 ₂ , 21 ₃ , and the frequency division phase shift circuits 21 ₀ , 21 ₁ , 21 ₂ , 21 ₃ Square wave signals fψ ₀ , fψ ₁ , fψ ₂ , and fψ ₃ are output individually. Such a frequency division phase shift circuit can be constructed from a 2-bit binary counter, a 4-bit shift register, or the like.

The selector circuit 24 outputs a signal fψ ₀ when the count value of the counter 23 is “0”, and outputs a signal fψ ₁ when the count value of the counter 23 is “1”.
When it is "2", the signal fψ ₂ is selected and when it is "3", the signal fψ ₃ is selected and output. As such a selector circuit, a commercially available IC selector circuit (for example, model number SN74153) can be used, and in this case, the data input terminal is connected to the frequency dividing and phase shifting circuits 21 ₀ , 21 ₁ , 21 ₂ , 21 ₃ and the input terminal for the data designation signal to the output terminal of the counter 23.

The adder circuit 3 is a known circuit using an arithmetic amplification circuit, and combines the output signal of the modulation circuit 14 and the filter 2.
Add the output signals of 5 in an analog manner.

The phases of the square wave signals fψ ₀ , fψ ₁ , fψ ₂ , fψ ₃ are
It advances by 90 degrees in the order of fψ ₀ , fψ ₁ , fψ ₂ , fψ ₃ ,
The frequency f is chosen to be higher than the frequency _F1 of the clock signal CP. Further, the frequency F ₁ of the clock signal CP is lower than the frequency F ₂ of the carrier wave signal used in the modulation circuit 14 .

In the above transmitter A, when the signal generating circuit 10 outputs the clock signal CP shown in FIG. 2A,
Since the bit counter 11 counts the clock signal CP and advances repeatedly, the data selector circuit 13
As shown in FIG. 2B, _the data output circuit 12 outputs each bit of information _{D 1 ,} D ₂ . ......A modulated wave signal corresponding to Dx is output. Furthermore, each time the count value of the bit counter 11 becomes zero, the flip-flop 22 is triggered and its output becomes a logic value "H" or "L" each time it outputs one word of data as shown in FIG. 2C. , the counter 23 alternately repeats the addition state and the subtraction state, and as a result, the selector circuit 24 outputs the rectangular wave signals fψ ₀ , fψ ₁ , fψ ₂ , fψ ₃ to the counter 22 as shown in FIG. 2D. While counting in the addition state, the signals fψ ₀ , fψ ₁ , fψ ₂ , fψ ₃ , fψ ₀ are repeatedly output in the order of 0, and while counting in the subtraction state, they are repeatedly output in the reverse order, thereby increasing the frequency. The filter 25 outputs a synchronizing signal whose phase is sequentially shifted by 90 degrees in synchronization with the clock signal at f. As a result, a signal obtained by adding the modulated wave signal and the synchronization signal is transmitted from the addition circuit 3 to the synchronization signal generation circuit 4 and reproduction circuit 5 of the receiver B.

The synchronization signal generation circuit 4 includes a band filter 30,
An amplifier 31 that amplifies the output signal, a circuit 32 that detects the phase of the output signal, and a detection circuit 3 using a diode to which the output signal of the phase detection circuit 32 is input via a coupling capacitor 33.
4, 35, and a circuit 3 that shapes the waveform of each detection output.
6, 37, an OR circuit 38 which outputs an OR signal of the output signals of both waveform shaping circuits 36, 37, and an OR circuit 38 which is set at the rising edge of the output signal of the waveform shaping circuit 36,
The flip-flop 39 is reset when the output signal of the waveform shaping circuit 37 rises.

The synchronization signal generation circuit 4 uses a filter 30 to extract the frequency f component of the synchronization signal from the input signal, amplifies it, and then detects the phase using a phase detection circuit 32. As a result, as shown in FIG. 2E, a signal corresponding to the phase change point of the transmitted synchronization signal can be obtained. This phase detection output is synchronized with the clock signal CP, and becomes a positive pulse when the synchronization signal is in a leading phase, and a negative pulse when it is in a lagging phase. As the phase detection circuit 32, a phase demodulator based on a phase lock loop circuit using a phase comparator, a low-pass filter, a voltage controlled oscillator, and an integrator can be used.

The synchronizing signal generation circuit 4 further extracts the positive side pulses in the output signal of the phase detection circuit 32 by the detection circuit 34, the negative side pulses by the detection circuit 35, and sends each extracted pulse to the waveform shaping circuit 3 of the next stage.
6 and 37, the signal is converted into the signals shown in FIG. 2, F and G. As a result, the output of the OR circuit 38 is F and G in FIG.
2, that is, the bit synchronization signal shown in FIG. 2I is obtained, and the word synchronization signal shown in FIG. 2H is obtained at the set output of the flip-flop 39. Since the bit synchronization signal is synchronized with the clock signal shown in FIG. 2A, it is synchronized with the timing of transmission of each bit of information. Further, the word synchronization signal has periods of logical value "H" and periods of "L" alternately, and each period is synchronized with the transmission period of data for one word.

The reproducing circuit 5 includes a band filter 40, an amplifier 41 that amplifies its output signal, a demodulator 42 that demodulates the amplified signal, and a decoder 43 that decodes transmitted information word by word. is a known circuit with a modulated carrier frequency from the input signal
After extracting and amplifying the _F2 component, the demodulator 4 uses a demodulation method according to the modulation method in the modulation circuit 14.
2, and then decodes the transmitted information word by word using the demodulated signal, a bit synchronization signal, and a word synchronization signal. The bit synchronization signal is used in the decoder 43 as a timing signal for storing transmitted information bit by bit in a shift register or buffer memory, and the word synchronization signal is used as a timing signal for decoding one word of data.

As described above, the present invention provides a fixed frequency that is phase-shifted by a predetermined angle in synchronization with the transmission of one bit of data and is controlled to lead phase and lagging phase in synchronization with the transmission of one word of data. The synchronization signal is added to the data to be transmitted and sent out, and the receiving side detects the change in the phase of the synchronization signal in the input signal to create a bit synchronization signal and a word synchronization signal. By simply transmitting different types of synchronization signals, mutually related bit synchronization signals and word synchronization signals can be obtained with a simple and inexpensive circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an electric circuit of an embodiment of a data transmitting/receiving device according to the present invention, and FIG. 2 is an explanatory diagram of electric signals. A: Transmitter, B: Receiver, 1: Transmission data conversion circuit, 2: Synchronization signal generation circuit, 3: Addition circuit,
4: synchronous signal generation circuit, 5: received data regeneration circuit.

Claims (1)

[Claims] 1. On the transmitting side, the phase is sequentially shifted by a predetermined angle in synchronization with the transmission of one bit of data, and the phase is controlled to lead and lag in synchronization with the transmission of one word of data. a circuit for generating a synchronization signal of a constant frequency, and means for adding and outputting the synchronization signal and the data to be transmitted; A data transmitting/receiving device equipped with a synchronization signal generation circuit that generates a bit synchronization signal and a word synchronization signal. 2. The synchronization signal generation circuit counts and steps a plurality of rectangular wave signal generation means having the same frequency and whose phase is sequentially shifted by a predetermined angle, and a clock signal synchronized with the timing of transmission of one bit of data, and an up/down counter that is switched from an addition state to a subtraction state and from a subtraction state to an addition state each time one word of data is transmitted; and a selector circuit that selects and outputs the rectangular wave signal based on the count value of the counter. 2. The data transmitting/receiving device according to claim 1, further comprising: a bandpass filter that passes a frequency component of the rectangular wave signal among the output signals of the selector circuit. 3. The rectangular wave signal generating means includes a means for generating a reference rectangular wave signal of a constant frequency, and a plurality of frequency dividing and transferring means for frequency dividing and phase shifting the reference rectangular wave signal, each frequency dividing and transferring means 3. The data transmitting/receiving device according to claim 2, wherein the amount of phase shift is sequentially different by a predetermined angle. 4 means for the synchronization signal generation circuit to extract the synchronization signal from the input signal and detect its phase;
A means for separately extracting the positive side pulse and negative side pulse of the phase detection signal, a circuit for outputting an OR signal of both the extracted pulses, and a flip-flop that is set by the extracted positive side pulse and reset by the extracted negative side pulse. Claim 1 having
3. The data transmitting/receiving device according to item 2, item 3, or item 3.