JPS6311819B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an independent synchronizer for converting signals of one signal system into the other signal system between two signal systems each processed by clocks operating completely independently.

There are three typical network synchronization techniques in a PCM integrated network where transmission and switching are integrated: dependent synchronization, mutual synchronization, and independent synchronization. In the independent synchronization system, the signal is phase modulated by a sawtooth wave having a frequency Δf, which is the difference between the sampling frequencies of two independent clock systems, and is sensed as splicing noise. Conventionally, a method of removing this splicing noise has been considered by using a memory circuit to move the splicing noise caused by the non-moving period to an instantaneous rest (pause) period that exists between signals. ing. However, when targeting data transmission, it is necessary to forcibly insert pauses, and since channels are multiplexed for audio signals, the above operation must be performed separately for each channel. The disadvantage was that it was very complicated to carry out.

Furthermore, recently, an independent synchronizer has been considered that uses digital signal processing technology to interpolate sample values other than the sample time and extract the interpolated sample value closest to the output sample time.

The present invention is an improvement on an independent synchronizer using a method of interpolating sample values. Therefore, first, the principle of an independent synchronizer using this interpolation method will be explained.

In the following explanation, the sampling frequency f ₁ Hz is an integer multiple (1
A data system operating at a sampling frequency f ₂ Hz (however, f ₂ is approximately equal to f ₁ ) is called a clock system 1, and a data system operating at an integer multiple (including 1) of the sampling frequency f 2 Hz (however, f 2 is approximately equal to f 1) is called a clock system. I'll call it 2. FIG. 1A shows a sample value sequence of an input signal sampled at a frequency _f1 , and when this input sample value sequence is relayed at a completely independent sampling frequency _f2 , _f1
If <f ₂ , the sample value series of the output signal will be as shown in FIG. 1B. The input sample value S _i1 is
The same output sample values S ₀₁ and S ₀₂ are output, resulting in data duplication. On the other hand, when f ₁ > f ₂ , data is dropped, and in either case, it causes splicing noise.

Therefore, as shown in Fig. 1C, from the input sample value series, sample values S _s (indicated by small black circles) other than that sampling point S _p (indicated by large black circles) are obtained.
is interpolated, and the value of the closest one among the original sample time S _p and the interpolated sample time S _s is extracted at the sample time of the sampling frequency f ₂ of the output signal. A series of output signals sampled in this manner is shown in FIG. 1D. The interpolation shown in FIG. 1C is performed by supplying an input sample value series to an interpolation digital filter having low-pass characteristics. In FIG. 1C, the sampling frequency f _F of the interpolation digital filter is 4×f ₁ Hz, and three points are interpolated during one sampling period. The larger f _F becomes, the more it becomes possible to reduce the splicing noise.

The analysis of coupling noise between two independent clock systems is described in detail in the paper ``Independent Synchronous PCM Relay System'' published in the Journal of the Institute of Electronics and Communication Engineers published in February 1964.

Now, let the sampling frequencies of the input signal and the output signal be f ₁ Hz and f ₂ Hz, respectively, and the difference between these two sampling frequencies be Δf. Further, if a single sine wave e ^j2 〓 ^f0t is considered as an input signal, the output signal a ₂ (t) is expressed as the following equation.

a ₂ (t) = _∞ 〓 ^P=-∞ S _p,o exp〔j2π(f ₀ +p△f −nf ₂ )t〕 (1) However, S _p,o =S _p,0 exp〔j2πf ₂ t ₀₂ ] (2) S _p,0 = sin {π(p+f ₀ /f ₁ )}/π(p+f ₀ /f ₁ )exp
[−jπ(p+f ₀ /f ₁ ) −j2πp△ft _c ] (3) t _c = (f ₁ t ₀₁ −f ₂ t ₀₂ )/△f (4) Here, t ₀₁ and t ₀₂ are respectively These are the initial values of the sample time on the input side and the sample time on the output side. Also, p is an integer, and the value of n takes only the value that satisfies |f ₀ +p△f−nf ₂ |<f ₂ /2 (5), so f ₀ and P
It is uniquely determined from.

The spectrum of the input signal with signal frequency f ₀ and sampling frequency f ₁ is as shown in Figure 2A, and it is expressed as f ₂
As shown in FIG. 2B, the spectrum of the output signal sampled in is centered on the original signal f ₀ and many sideband waves are generated at intervals of Δf. If these sideband components are regarded as distortion components, the signal-to-noise ratio can be expressed as follows.

S/N=|sin(πf ₀ /f ₁ )/(πf ₀ /f ₁ )| ² /1−|
sin (πf ₀ /f ₁ ) / (πf ₀ /f ₁ ) | ² (6) As is clear from equation (6), when the input frequency is zero, the denominator of S/N becomes zero, and S/N is infinite, but gradually deteriorates as it approaches 1/2 of the sampling frequency f ₁ Hz, that is, the highest frequency of the input signal. If the input signal frequency is constant, the S/N increases as the sampling frequency f ₁ increases.

FIG. 3 shows an example in which an interpolation digital filter is provided to equivalently increase the sampling frequency f ₁ Hz to improve the S/N ratio. An input signal having a sampling frequency f ₁ Hz inputted from an input terminal 11 is inputted to an interpolation digital filter 12, and a sample value series at a rate of K×f ₁ Hz is output. The sampling frequency of the interpolation digital filter 12 is K×f ₁ Hz, and it has a low-pass characteristic that attenuates the harmonics of the input signal with the sampling frequency f ₁ Hz and extracts only the input signal frequency components. It is. Interpolation digital filter 1
The output data of No. 2 is input to the clock system conversion circuit 13, and is converted from the K×f ₁ Hz sample rate to the K×f ₂ rate. The output data of the clock conversion circuit 13 is taken out once every K times by the switch 14 and outputted to the output terminal 15. In other words, switch 1
4 operates to capture data every f ₂ Hz. Therefore, data at the sampling frequency f ₂ Hz is obtained at the output terminal 15.

In the independent synchronization method that interpolates sample values with such a configuration, the ratio of input frequency to sampling frequency f ₀ /f ₁ in equation (6) becomes f ₀ /(K × f ₁ ), and S /N can be improved. However, in order to fully obtain this improvement effect, the value of K must be made considerably large. As is clear from calculating equation (6), f ₁ = f ₂ = 8K
Hz, K=32 for input signal frequency f ₀ =3KHz
However, the S/N is only about 33dB. For example, in voice PCM communication, a S/N of about 35 dB is required, so the above-mentioned splicing noise must be sufficiently larger than 35 dB, and the S/N must be increased to 45 dB.
To do this, we must also set K to 128. Furthermore, considering the characteristics of the interpolating digital filter 12 and the effects of rounding noise (noise caused by matching the number of output bits of the multiplier to the number of input bits), K must be set to a very large value. The disadvantage is that the circuit scale becomes large.

SUMMARY OF THE INVENTION An object of the present invention is to provide an independent synchronizer that can reduce splicing noise using digital signal processing. Another object of the present invention is to provide an independent synchronizer with low coupling noise and a small circuit scale.

According to the independent synchronizer of this invention, the sampling frequency
The input signal of f ₁ has a sampling frequency of K×f ₁ Hz (K
is an integer of 2 or more), and the sample value series of clock system 1, which is this output series, is converted into the sample value series of clock system 2 by clock system converting means. This converted sample value series has a sampling frequency of K′×f ₂ Hz
(where K'=K+1 or K'=K-1), the signal is supplied to a low-pass digital filter with a cutoff frequency of f ₂ /2 Hz, and sideband components that become noise are removed by this filter. The output series of this low-pass digital filter is taken out every K′, and the sampling frequency f ₂
Obtain an example of the output sample value system in Hz.

As is clear from equation (1), when sampling a signal with sampling frequency f ₁ at frequency f ₂ , in addition to the original signal, △f
It has an infinite number of sideband waves at an interval of = f ₁ to f ₂ , and these become splicing noise. Now, the input signal band is 0 to 4KHz, the sampling frequency of the input signal is f ₁ = 8KHz,
Let the sampling frequency of the output signal be f ₂ =8KHz. However, f ₁ and f ₂ are completely independent. Further, consider as an example the case where the sampling frequency of the interpolation digital filter is K×f ₁ =64 KHz, that is, K=8.

Consider the sampling frequency K'×f ₂ Hz in clock system 2. However, K′ is a positive integer. As an example
Considering K′×f ₂ =72KHz, that is, K′=9, the difference △f between the sampling frequency Kf ₁ (=64KHz) and K′f ₂ (=72KHz)
is 8KHz, and a signal with a certain frequency f ₀ Hz (however, 0
<f ₀ <4KHz), the spectrum of the output signal is arranged at 8KHz intervals as shown in FIG. 4A. In the clock conversion circuit 13, K′f ₂ =72K
Since the sampling frequency is Hz, its effective signal component is below Kf ₂ /2 = 36 KHz, and sideband components higher than that are folded back at K'f ₂ /2. However, as shown in Figure 4B, the sampling frequency K'×f ₂ = 72KHz
If a low-pass digital filter with a cutoff frequency of 4 KHz is used, most sideband waves other than those falling in the -4 to 4 KHz band can be suppressed. In this way, since Δf is set to a frequency that is more than twice the maximum frequency of the input signal frequency, 4 KHz, no low-order sideband components enter the baseband. K and
Since the difference with K' is set to 1, the folded sideband components, especially those that fall into the baseband, have a high sideband order and a low level. Therefore, by using the low-pass filter, the S/N ratio can be improved even if K is made relatively small.

FIG. 5 shows an embodiment of the present invention, and parts corresponding to those in FIG. 3 are designated by the same reference numerals. In this invention, the output of the clock conversion circuit 13 is K′×f ₂
The signal is passed through a low-pass digital filter 17 with a cutoff frequency of f ₂ /2, and its output series is taken out every K' by a switch 14.

The interpolation digital filter 12 can be realized, for example, by a recursive digital filter or a non-recursive digital filter. This filter 1
The sampling frequency of the input signal in step 2 is f ₁ Hz, which is 1/K of the operating frequency K x f ₁ Hz, and the input signal only needs to be input once every K times, so if the filter decomposition method is used, , the circuit scale can be reduced.
This filter decomposition method is described in the publication ``IEEE TRANSACTION ON'' published in August 1974.
ACOVSTICS, SPEECH, and SIGNAL
PROCESSING VOL.ASSP−22, No.4”
The paper “Interpolation,” on pages 231 to 235,
Extvapolation, and Reduction of Computation
Speed in Digital Filters”.

FIG. 6 shows a detailed block diagram of the clock system conversion circuit 13, and its operation will be explained in detail with reference to the timing chart shown in FIG. In FIG. 6, a sample value series 131 with a sampling frequency Kf ₁ is directly supplied to a selector 133 and simultaneously supplied via a 1/2 sample delay element 132. 2 supplied to these selectors 133
The timing charts of the sample value series are shown in FIGS. 7A and 7B, respectively. A corresponds to the sample value series 131 and B corresponds to the 1/2 sample delay element 13
This corresponds to the sample value series of output No. 2. However, in A and B, numbers are assigned to each sample value in order. Figures 7C and 7D show the timing of Kf ₁ clock 137 and K'f ₂ clock 138, respectively. These two clocks are input to phase comparator 136 and the clock phases are compared as follows. That is, the phase comparator 136 outputs "0" when the difference between the two is in the range of 1/4 clock to 3/4 clock, and otherwise outputs "1", which is supplied to the selector 133. The selector 133 indicates that the phase comparator 136 is “0”
When it is "1", sample value series 131 is used, and when it is "1", it is 1/2.
The output of the sample delay element 132 is selected and output, and is supplied to a D-type flip-flop 134. A K'f ₂ clock 138 is supplied as a clock to the D-type flip-flop 134, and clock system conversion is performed by retiming the data of clock system 1 with the clock of clock system 2. 7E and 7F show timing charts of the output of the phase comparator 136 and the output sample value series 135 of the D-type flip-flop 134, respectively. Note that FIG. 7 shows an example where Kf ₁ <K'f ₂ as is clear from the clock phase relationship between C and D. Therefore, the sample value series 135 after clock conversion shown in FIG. Duplication (sample value number 5 appears twice) occurs. The relationship between the input and output sample value series shown in FIG. 7 corresponds to the relationship between A and B in FIG. However, it is necessary to regard the sampling frequencies of the sample value series as Kf ₁ and K'f ₂ in FIGS. 1A and 1B, respectively. The block diagram in FIG. 6 has a configuration that provides sufficient timing margin for the operation of the D-type flip-flop 134, but if it is an ideal D-type flip-flop that does not require or can ignore the timing margin, The /2 sample delay element 132, selector 133 and phase comparator 136 can be removed, and the sample value series 131 can be directly supplied as the data input to the D-type flip-flop. Next, we return to the explanation of FIG.

The output of the clock conversion circuit 13 is subjected to a low-pass digital filter 17, in which sidebands of f ₂ /2 or more are suppressed. The output K′×f ₂ Hz sample rate data is extracted once every K′ times by the sample rate conversion switch 14 that operates every f ₂ Hz.
Data at the sampling frequency f ₂ Hz is obtained at the output terminal 15. Next, the configurations of the interpolation digital filter 12 and the low-pass filter 17 shown in FIG. 5 will be described. The configurations of both filters may be basically the same. FIG. 8 is a block diagram showing an example of the configuration of an interpolation digital filter or a low-pass filter. FIG. 8A shows a block diagram when a non-recursive digital filter is used, and FIG. 8B shows a block diagram when a recursive digital filter is used.

In FIG. 8A, reference numerals 811, 812,
813 and 814 are delay elements for one sample, reference numbers 821, 822, 823, 824, 825
and 826 indicate a multiplier. Also reference number 800
1 indicates an input terminal, and reference numeral 8002 indicates an output terminal.

In Figure 8B, reference numerals 841, 842 and 843 are one sample delay elements, reference numeral 85
1,852,853,854,861,862,
863, 864 and 865 are multipliers. Furthermore, reference number 8003 is an input terminal, reference number 800
4 indicates an output terminal.

As mentioned above, it is clear that the sampling frequency difference Δf when converting the clock system must be greater than f ₁ Hz or f ₂ Hz to prevent sideband components from entering the baseband region, and It is appropriate to select K' to a value that satisfies the following equation so that the sideband wave that is folded back into the baseband becomes a high-order component and has a sufficiently small level.

K'=K±1 (7) Furthermore, K may be selected so as to satisfy the given S/N standard, but it goes without saying that K must be 2 or more due to the nature of interpolation.

The output rate of the low-pass digital filter 17 is K'×f ₂ Hz, but due to the sample rate conversion switch 14, data is output to the output terminal 15 only once every K' times, so as mentioned earlier, By using a digital filter decomposition technique, the circuit scale of the low-pass digital filter 17 can be reduced.

As described above, according to the present invention, it is possible to reduce connection noise and provide an independent synchronizer with a small circuit scale.

[Brief explanation of the drawing]

Figure 1 is a diagram to explain the principle of an independent synchronizer using sample value interpolation, Figure 2 is a diagram showing the input spectrum and output spectrum of the independent synchronizer, and Figure 3 is an example of an independent synchronizer using sample value interpolation. FIG. 4 is a diagram for explaining the principle of the invention, FIG. 5 is a block diagram showing an embodiment of an independent synchronizer according to the invention, and FIG. 6 is a block diagram of a clock system conversion circuit. , FIG. 7 is a timing chart for explaining the operation of FIG. 6, and FIG. 8 is a block diagram of the interpolation digital filter 12 or low-pass filter 17 of FIG. 5. 11: input terminal, 12: interpolation digital filter, 13: clock system conversion circuit, 14: sampling rate conversion switch, 15: output terminal, 17: low-pass digital filter.

Claims (1)

[Claims] _{1. A first clock system that processes a signal sampled at a sampling frequency f 1 at} a speed that is an integer multiple (including 1) of _{f 1 ;} In a system in which the second clock system operates completely independently of the second clock system, which processes the signal sampled at the sampling frequency f ₁ at an integer multiple (including ₁ ) of f 2 , A sampled signal is supplied, and the sampling frequency is K×f ₁ (K is an integer greater than or equal to 2)
a low-pass interpolation digital filter that operates at
A clock system conversion means converts the clock system sample value sequence into the second clock system sample value sequence, and the converted sample value sequence is supplied, and the sampling frequency is K′×f ₂ (K′ and K The difference is that it works in 1),
A low-pass digital filter with a cutoff frequency of f ₂ /2 and the output series of the low-pass digital filter.
an independent synchronizer having means for taking out every K′;