JPS63117594A - Dropout processing circuit - Google Patents

Abstract

PURPOSE:To attain low cost and space saving by converting two color difference signals fed individually into a serial alternate signal so as to apply dropout compensation processing of a 2-system signal by one line delay circuit only. CONSTITUTION:A changeover switch 208 is switched at the production of dropout, its output is fed to a 1H delay circuit 207 and a 1H delay output is selected by the switch 208 at dropout to compensate the missing of signal. A dropout pulse S76 whose time base is doubled obtained from an output of a memory 214 is supplied to the switch 208 via a parallel/serial converter 215 and a latch 216. Thus, the output S69 of the switch 208 is replaced by an output of the circuit 207 in the dropout period synchronized with a reference clock and the missing part is compensated by the signal of the adjacent line.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dropout processing circuit for video signals, and particularly to video tape recorders and the like that record and reproduce a luminance signal and two color difference signals R-Y and B-Y. This applies to

[Summary of the invention]

By converting two individually supplied color difference signals into serial alternating signals, it is possible to perform dropout compensation processing for two-system signals using only - line delay circuits.

[Conventional technology]

2. Description of the Related Art A TV camera with a VTR that records and reproduces a luminance signal and a color difference signal separately is known. As is well known, in a VTR, dropout occurs in which the reproduced carrier is partially lost due to dust or scratches on the magnetic tape. As a dropout compensation circuit, an IH line memory that stores one line of the reproduced signal is provided, and when a dropout is detected, that part of the reproduced signal is switched to the output of the line memory to make the loss less noticeable. It has been known. A VTR that records color difference signals as described above is provided with two systems of dropout compensation circuits.

[Problem that the invention seeks to solve]

Dropout compensation circuitry requires expensive IH line memory. SUMMARY OF THE INVENTION An object of the present invention is to reduce cost and save space by converting two lines of line memory into one line memory.

[Means for solving problems]

The dropout processing circuit of the present invention includes a conversion circuit that converts two individually supplied color difference signals R-Y and B-Y into a serial alternating signal, and a delay circuit that delays the serial alternating signal by one horizontal scanning period. , a changeover switch that switches from the serial alternating signal to the output of the delay circuit in a section where a signal dropout occurs, and a conversion circuit that converts the serial alternating signal output from the changeover switch into two individual color difference signals. do.

〔Example〕

FIG. 1 shows a dropout processing circuit according to an embodiment of the present invention. The signal given to input terminal T1 is 313 in FIG.
This is a signal obtained by digitizing the VTR playback output of the time-base compressed color difference signal shown in FIG. In the VTR camera with VTR of this embodiment, the seedness signal (5ll in FIG. 2) and the color difference signal R-Y
, B-Y (312.514 in Fig. 2) are FM recorded on separate tracks, and the color difference signals are recorded as 313 in Fig. 2.
As shown in the figure, the time axis is compressed to 1/2 and recording is performed alternately every 1/2 horizontal section.

As shown at 321 in FIG. 3, when a dropout a occurs in the reproduced RF signal of the color difference corresponding to 313 in FIG. Dropout compensation can be performed by replacing the reproduced signal with the output of the IH line memory. But if you do it like this,
Since only one of the sequences RY and B-Y is compensated, it is incomplete and unnatural. Therefore, Fig. 3 325, S
For both of the color difference signals which are time-expanded twice as shown in 26 and are synchronized, sections C and d are compensated for using a dropout pulse (S24) which is also time-expanded.

Therefore, in FIG. 1, the digital time-compressed color difference signal S61 applied to the input terminal TI passes through the serial-parallel converter 201, is stored in the memory 202, and is read out with the time axis doubled.

The time chart in FIG. 4 shows the read-side reference clock RCK (S81) corresponding to the write clock and the read clock 1/2 RCK (S80) with a double period thereof. Similarly, the dropout pulse (
S74) also passes through the serial-to-parallel converter 213, is stored in the memory 214, is expanded on the time axis, and is read out.

Note that the memory 202 also has the function of a time base collector, and performs time base correction by modulating the write clock with jitter and fixing the read clock RCK. The readout output (8 samples/parallel) of the memory 202 is branched and supplied to parallel-to-serial converters 203 and 204 as R-Y and BY simultaneous signals, respectively, and the fourth
The signals are converted into serial signals (R-Y and B-Y simultaneously) of one sample (8-bit configuration) shown in FIGS. S64 and S65.

The output of each parallel-serial converter 203 and 204 is supplied to a changeover switch 205, and the reference clock RCK (
By switching the selector switch 205 in response to the high level/low level of S80), a sequential signal (S80) in which R-Y and B-Y alternate within one sample cycle as shown in FIG. 4 366 is generated. (serial alternating signal). The output of the changeover switch 205 is latched in the latch 206 using the reference clock RCK (S81) as shown in FIG. 4 367, and then output to the changeover switch 208.

The selector switch 208 is switched when a dropout occurs, and its output is supplied to the IH delay circuit 207, and the IH delay output (868 in FIG. 4) is selected by the switch 208 at the time of a dropout to compensate for signal loss. ing. This selector switch 208 is connected to a dropout pulse S76 obtained from the output of the memory 214 described above, which is obtained by doubling the time axis.
t5 (output 577) and latch 216 (output 578
). Therefore, in the dropout period synchronized with the reference clock RCK (S81) as shown in FIG. 4, the output S69 of the changeover switch 208 is the output (R-Y )' (B-Y) ', and the missing part is complemented with the signal of the adjacent line.

In this way, dropout processing for two systems of color difference signals is possible with only one IH delay circuit 207. Note that the IH delay circuit 207 can be configured with a 910-stage shift register in the case of 4fsc sampling (four times the frequency of the subcarrier).

The output (S69) of the changeover switch 208 is the latch 209.
At 210, the signals are latched at the rising and falling edges of the read clock 380 as shown in FIG. Inverter 217 is for inverting the latch phase. Each latch 2
The output of 09.210 is latched again with the lid clock S80 in the latch 211.212, and the output of 372 in FIG.
As shown in S73, the phase is matched and the synchronized color difference signal R-
Y, B−Y.

Note that by manipulating the address of the memory 202, R-Y and B
-Y color difference sequential signals may be read out and dropout processing may be performed.

For reference, FIG. 5 shows the configuration of a conventional dropout processing circuit, and FIG. 6 shows an operation time chart. As shown in the figure, conventionally two systems of IH delay circuits 107 and 108 were required. In FIG. 5, 101.113 is a serial-parallel converter, and 102
．． 114 is a memory, and 103, 104, and 115 are parallel-to-serial converters, which correspond to those shown in FIG. Further, 105.106.116.111.112 is a latch, and 109.110 is a changeover switch. In FIG. 6, S51 is a reference clock on the read side, 350 is a read clock, S34 and S35 are parallel-to-serial conversion outputs, and S36 and S38 are R and -Y main line signals and IH
S47 and 348 are dropout pulses, S40 is the dropout compensated output of the switch 109, and S42 and S43 are the dropout processing outputs RY and BY.

〔Effect of the invention〕

As described above, in the present invention, when performing the dropout processing of the two-system color difference signal, the processing is performed after converting it into a serial alternating signal, so that only one expensive line delay circuit is required, thereby reducing cost and space.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a dropout processing circuit according to an embodiment of the present invention, FIG. 2 is a format diagram of a recording signal in a VTR according to the embodiment, FIG. 3 is a waveform diagram showing the operation of dropout compensation, and FIG. The figure is the operation time chart of Figure 1, and the operation time chart of Figure 5.
The figure is a circuit diagram of a conventional dropout processing circuit, and FIG. 6 is an operation time chart of FIG. 5. In addition, in the reference numerals used in the drawings, 205...--1----------...- Selector switch 207-------... IH delay circuit 208--...-・---111---It is a switching switch.

Claims (1)

[Claims] a conversion circuit that converts two individually supplied color difference signals into a serial alternating signal; a delay circuit that delays the serial alternating signal by one horizontal scanning period; A dropout processing circuit comprising a changeover switch for switching to the output of a delay circuit, and a conversion circuit for converting a series alternating signal output from the changeover switch into two separate color difference signals.