JPS63117333A - Semiconductor laser driving circuit - Google Patents

Semiconductor laser driving circuit

Info

Publication number
JPS63117333A
JPS63117333A JP61263271A JP26327186A JPS63117333A JP S63117333 A JPS63117333 A JP S63117333A JP 61263271 A JP61263271 A JP 61263271A JP 26327186 A JP26327186 A JP 26327186A JP S63117333 A JPS63117333 A JP S63117333A
Authority
JP
Japan
Prior art keywords
semiconductor laser
circuit
current
output
erasure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61263271A
Other languages
Japanese (ja)
Inventor
Takao Miyazawa
孝雄 宮澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP61263271A priority Critical patent/JPS63117333A/en
Publication of JPS63117333A publication Critical patent/JPS63117333A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To perform accurate erasure without rounding the driving current of a semiconductor laser by providing an erasure current driving circuit which drives an erasure current by such a way that it is added to a bias current when the operation of the semiconductor laser is changed from a playback state to an erasure state or vice versa. CONSTITUTION:This circuit is equipped with a pulse current driving circuit 7 which applies a pulse current to the semiconductor laser with a recording signal, the erasure current driving circuit 7 which supplies a current to the semiconductor laser at the time of erasure, and an I-V converting amplifier circuit 3 which converts and amplifies a current signal from a monitor photodiode for monitoring the light output of the semiconductor laser to a voltage value. Further, this is equipped with an adding circuit 4 which adds the outputs of reference voltage generating circuits 1, 2, and 3, a differential amplifier circuit 5 which compares the output of the I-V converting amplifier circuit 3 with the output of the adding circuit 4, and a bias current driving circuit 6 which supplies the bias current to the semiconductor laser with the output of the differential amplifier circuit 5. The erasure current and bias current are added and applied by the erasure current driving circuit 7, so the transient response from the playback state to the erasure state is not rounded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体レーザにより記録、再生及び消去を行
う光学式記録再生装置の半導体レーザ駆動回路に関する
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor laser drive circuit for an optical recording/reproducing device that performs recording, reproduction, and erasing using a semiconductor laser.

〔従来の技術〕[Conventional technology]

半導体レーザを光源として用いた光学式情報記録再生装
置では、情報再生時においては半導体し−ザの光出力が
一定に保たれるように、半導体レーザへ供給するバイア
ス電流を制御する。(以下ムP C: Astomat
ia X’ower Controlと呼ぶ、)また情
報記録時においては、記録信号で半導体レージを直流バ
イアスにパルス電流を重畳する形式でパルス駆動するの
が一般的である。
In an optical information recording/reproducing apparatus using a semiconductor laser as a light source, a bias current supplied to the semiconductor laser is controlled so that the optical output of the semiconductor laser is kept constant during information reproduction. (Hereinafter referred to as PC: Astomat
When recording information, it is common to pulse-drive a semiconductor laser using a recording signal in a manner that a pulse current is superimposed on a DC bias.

第2図は従来の半導体レーザ駆動回路図である。FIG. 2 is a conventional semiconductor laser drive circuit diagram.

半導体レーザlの光出力はモニターホトダイオード2で
モニタされ、電流信号として検出される。
The optical output of the semiconductor laser 1 is monitored by a monitor photodiode 2 and detected as a current signal.

演算増幅器21と、抵抗22で構成される1→V変換増
幅回路で電圧直へ変換して、光出力モニタ信号を侍る。
A 1→V conversion amplification circuit composed of an operational amplifier 21 and a resistor 22 converts the signal into a direct voltage, and serves as an optical output monitor signal.

ローパスフィルタ28はAPCループの帯tj!/、を
制限するとともに、記録時においては記録信号でパルス
駆動された半導体レーザlの光出力の平均直をモニタす
るように記録信号帯域はカットする動作を行う、信号再
生時にはスイッチ24は再生出力基準電圧25と接続さ
れていて、この電圧と光出力モニタ信号24とが差動増
幅器5により比較されて%ローパスフィルタ2Bを通っ
た後、トランジスタ29のペースに印加される。
The low-pass filter 28 is connected to the band tj! of the APC loop. /, and at the time of recording, the recording signal band is cut so as to monitor the average directivity of the optical output of the semiconductor laser l pulse-driven by the recording signal. During signal reproduction, the switch 24 controls the reproduction output. It is connected to a reference voltage 25, and this voltage and the optical output monitor signal 24 are compared by the differential amplifier 5 and applied to the pace of the transistor 29 after passing through the % low-pass filter 2B.

トランジスタ29と抵抗30によりミ流源が構成されて
いて、半導体レーザ1にバイアス電流を供給する。この
Arcループにより半導体レーザ1の光出力が一定とな
るように制御が行われる。
The transistor 29 and the resistor 30 constitute a current source, which supplies a bias current to the semiconductor laser 1. Control is performed by this Arc loop so that the optical output of the semiconductor laser 1 is constant.

次に情報記録時の回路動作について説明する。Next, circuit operation during information recording will be explained.

端子12から記録信号13が入力され、バッファ34と
イ/パータ33を介してトランジスタ31と32が交互
にスイッチングされる。トランジスタ35と抵抗36と
スイッチ37とパルス電流設定用基準電圧38とで定電
流源が構成されている。
A recording signal 13 is input from a terminal 12, and transistors 31 and 32 are alternately switched via a buffer 34 and an outputter 33. A constant current source is configured by the transistor 35, the resistor 36, the switch 37, and the pulse current setting reference voltage 38.

再生時にはスイッチ37はVCCに、記録時にはパルス
電流設定用基準電圧38に接続されるよりに動作する。
The switch 37 operates by being connected to VCC during reproduction and to the pulse current setting reference voltage 38 during recording.

記録イム号13が・・イレベルの時にはトランジスタ3
1がオン、トランジスタ32はオフとなり、ローレベル
の時には逆にトランジスタ31がオフ、トランジスタ3
2オンとなり、半4体レーザlにはパルス電流が印加さ
れる。一方スイッチ24は記録時には記録出力基準電圧
26と接続されていて、この電圧と光出力の平均直をモ
ニタしたモニタ信号25とを差動増幅器5で差をとり、
光°出力の平均喧が一定となるようにバイアス電流の制
御をおこなう。
When record im No. 13 is level...transistor 3
1 is on, transistor 32 is off, and when the level is low, conversely, transistor 31 is off, transistor 3 is off.
2 is turned on, and a pulse current is applied to the half-four body laser l. On the other hand, the switch 24 is connected to a recording output reference voltage 26 during recording, and the differential amplifier 5 calculates the difference between this voltage and a monitor signal 25 that monitors the average directivity of the optical output.
The bias current is controlled so that the average light output is constant.

また消去時においては、スイッチ24は消去出力基準電
圧27と接続されていて、再生時と同様に光出力モニタ
信号24と差動増幅器5で比較することによフ、APC
動作をおこなう。
Further, during erasing, the switch 24 is connected to the erase output reference voltage 27, and the differential amplifier 5 compares the optical output monitor signal 24 with the erase output reference voltage 27 in the same way as during reproduction.
Perform the action.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、前述の従来技術では半導体レーザの動作を再生
状態から消去状態へまたはその逆に変化させる時に第3
図に示すように、ローパスフィルタ28による帯域制限
のためIC1半導体レーザに印加される電流はなまった
波形となる。その結果、消去すべき領域の最初の部分が
消えのこりてしまりたシ、消去してはいけない頭載を消
去してしまうという問題点を生ずる。
However, in the prior art described above, when changing the operation of the semiconductor laser from the reproducing state to the erasing state or vice versa, the third
As shown in the figure, the current applied to the IC1 semiconductor laser has a rounded waveform due to band limitation by the low-pass filter 28. As a result, the problem arises that the first part of the area to be erased is left unerased, and the initial part that should not be erased is erased.

そこで1本発明は従来のこの様な問題点を解決するもの
で、その目的とするとζろは消去したい領域だけを正確
に消去することができる半導体レーザ駆動回路を提供す
ることにある。
One object of the present invention is to solve these conventional problems, and its purpose is to provide a semiconductor laser drive circuit that can accurately erase only the region desired to be erased.

c問題点を解決するための手段〕 本発明は、半導体レーザにより記録、再生及び消去を行
う光学式記録再生装置の半導体レーザ駆動回路において
、記録信号によりバルス電流を半導体レーザに印加する
パルス電流駆動回路と、消去時に半導体レーザに電流を
供給する消去電流駆動回路と、半導体レーザの光出力を
モニタするモニタホトダイオードからの電流信号を電圧
直に変換増幅するI→V変換増幅回路と、再生時の半導
 ・体レーザの光出力を設定するための電圧を発生する
基準電圧発生回路1と、前記記録信号により記録時の半
導体レーザの光出力を設定するための電圧を発生する基
準電圧発生回路2と、消去時の半導体レーザの光出力を
設定するための電圧を発生する基準電圧発生回路3と、
前記基準電圧発生回路1と、前記基準電圧発生回路2と
、前記基準電圧発生回路3からの出力を加算する加算回
路と。
Means for Solving Problem c] The present invention provides a pulse current drive for applying a pulse current to the semiconductor laser according to a recording signal in a semiconductor laser drive circuit of an optical recording/reproducing device that performs recording, playback, and erasing using a semiconductor laser. circuit, an erase current drive circuit that supplies current to the semiconductor laser during erasing, an I→V conversion amplifier circuit that directly converts and amplifies the current signal from the monitor photodiode that monitors the optical output of the semiconductor laser to a voltage, and A reference voltage generation circuit 1 that generates a voltage for setting the optical output of a semiconductor laser; and a reference voltage generation circuit 2 that generates a voltage for setting the optical output of the semiconductor laser during recording based on the recording signal. and a reference voltage generation circuit 3 that generates a voltage for setting the optical output of the semiconductor laser during erasing.
an adder circuit that adds outputs from the reference voltage generation circuit 1, the reference voltage generation circuit 2, and the reference voltage generation circuit 3;

前記■→V変換増幅回路の出力と、前記加算回路の出力
の比較をする差動増幅回路と、前記差動増幅回路からの
出力により、半導体レーザにバイアス電流を供給するバ
イアス電流駆動回路からなることを特徴とする。
It consists of a differential amplifier circuit that compares the output of the ■→V conversion amplifier circuit and the output of the adder circuit, and a bias current drive circuit that supplies a bias current to the semiconductor laser using the output from the differential amplifier circuit. It is characterized by

〔作用〕[Effect]

本発明の上記の構成によれば、情報消去時には半導体レ
ーザに消去電流駆動回路により、消去電流とバイアス電
流がプラスされて印加されるため、再生状態から消去状
態への過渡応答のなまらない半導体レーザの駆動が可能
となる。
According to the above configuration of the present invention, when erasing information, the erasing current drive circuit applies an erasing current plus a bias current to the semiconductor laser, so that the semiconductor laser has no dull transient response from the reproduction state to the erasing state. It becomes possible to drive.

〔実施列〕[Implementation row]

第1図は本発明の半導体レーザ駆動回路のブロック図、
第4図は本発明の一実施列の具体的な回路図である。従
来列の第2図と同一のものに関しては、図中同一番号で
表示しである。以下図面に基いて詳細に説明する。
FIG. 1 is a block diagram of a semiconductor laser drive circuit of the present invention,
FIG. 4 is a specific circuit diagram of one embodiment of the present invention. Components in the conventional column that are the same as those in FIG. 2 are designated by the same numbers in the figure. A detailed explanation will be given below based on the drawings.

端子12には記録信号13が、端子14にはイレーズ信
号15が、端子16にはリード信号17がそれぞれ入力
される。イレーズ信号15は消去時にa Haとなり、
それ以外は”Llとなっている。リード信号エフは半導
体レーザを発光させる時に’El状態となっていて、発
光させない時はl L lとなっている。また、記録信
号13は記録媒体上に記録されるピット有シが111に
、ピット無しが101に対応するデジタル信号である。
A recording signal 13 is input to the terminal 12, an erase signal 15 is input to the terminal 14, and a read signal 17 is input to the terminal 16. The erase signal 15 becomes aHa during erasing,
Otherwise, it is "Ll". The read signal F is in the 'El state when the semiconductor laser emits light, and is in the "Ll" state when it does not emit light. Also, the recording signal 13 is on the recording medium. The digital signal corresponds to 111 for recorded pits and 101 for no pits.

半導体レーザ1の光出力をモニタホトダイオード2でモ
ニタして得られた電流信号を、演算増幅器21と、抵抗
22で構成されるI→V変換増幅回路で電圧f直へ変換
する。39は反転増幅器で、Al’Cルーズの極性を合
わせている。光出力モニタ信号18と基準電圧40とを
差動増幅回路5で、差ヲとる。ローパスフィル28はA
PCループの帯威を制限している。11は基準電圧発生
回路2で、スイッチ53と演算増幅器54と抵抗51・
52と電圧源50から構成されている。スイッチ53は
列えはアナログスイッチ等で構成されていてイレーズ信
号1が11i1の時にONとなる。その時演算増幅器5
4で構成されたバッファの出力には、抵抗51と抵抗5
2で分圧された電圧直がえられる。仁の匝が消去時にバ
イアス電流に加算する消去電流を決定する。演算増幅器
59で前述のローパスフィルタの出力と、基準電圧発生
回路110出力を加算する。抵抗30とトランジスタ2
9で電流源を構成していて、これは第1図中のイレーズ
電流駆動回路6と消去電流駆動回路8をかねている。信
号再生時の動作は、従来列と同一である九め説明を省略
する。
A current signal obtained by monitoring the optical output of the semiconductor laser 1 with a monitor photodiode 2 is converted into a direct voltage f by an I→V conversion amplifier circuit composed of an operational amplifier 21 and a resistor 22. 39 is an inverting amplifier, which matches the polarity of the Al'C loose. The difference between the optical output monitor signal 18 and the reference voltage 40 is taken by the differential amplifier circuit 5. Low pass filter 28 is A
Limits the power of the PC loop. 11 is a reference voltage generation circuit 2, which includes a switch 53, an operational amplifier 54, and a resistor 51.
52 and a voltage source 50. The switch 53 is composed of an array of analog switches and the like, and is turned on when the erase signal 1 is 11i1. At that time operational amplifier 5
At the output of the buffer composed of 4, there are resistors 51 and 5.
The voltage divided by 2 can be obtained directly. The eraser determines the erase current to be added to the bias current during erase. An operational amplifier 59 adds the output of the aforementioned low-pass filter and the output of the reference voltage generation circuit 110. Resistor 30 and transistor 2
9 constitutes a current source, which also serves as erase current drive circuit 6 and erase current drive circuit 8 in FIG. The operation during signal reproduction is the same as that of the conventional array, so a detailed explanation will be omitted.

次に信号記録時の動作について説明する。Next, the operation during signal recording will be explained.

パルス電流駆動回路7の動作は従来列と同一である。第
4図中1点線で囲った部分10が基準電圧発生回路2で
ある。端子12からは記録信号137:)E入力さhる
。41はτTLのオープンコレクタタイプのバッファ(
例えば74L807)であシ。
The operation of the pulse current drive circuit 7 is the same as in the conventional column. A portion 10 surrounded by a dotted line in FIG. 4 is the reference voltage generation circuit 2. A recording signal 137:)E is input from the terminal 12. 41 is a τTL open collector type buffer (
For example, 74L807).

入力がローレベル時には出力はGNDに接地され。When the input is low level, the output is grounded to GND.

ハイレベル入力時には、出力はオープンの状態となる。When high level is input, the output is in an open state.

48は演算増幅器である。抵抗42の直をR1,抵抗4
3の直をR2とすると、入力信号13がローレベル時は
バッファ41の出力はOvとなり、ハイレベル時はvc
cf抵抗42・43で分圧した直、すなわち ”Ic c*R2/(R1+R2) となる。
48 is an operational amplifier. R1 is the direct line of resistor 42, resistor 4
3 is R2, the output of the buffer 41 is Ov when the input signal 13 is low level, and vc when the input signal 13 is high level.
The voltage is directly divided by the cf resistors 42 and 43, that is, "Icc*R2/(R1+R2)."

次に、抵抗44の直′f、R3,抵抗46のIl!をR
4、抵抗47の値上R5,コンデンサ45のflIIを
Cとする。抵抗44とコンデンサ45でローパスフィル
タが作られている。このローパスフィルタはモニタホト
ダイオード2及び、1→V変換増幅回路によるローパス
と同じ特性を持たせ、カットオフ周波数IPcは。
Next, the directivity 'f of the resistor 44, R3, and Il of the resistor 46! R
4. Let R5 be the value of the resistor 47, and flII of the capacitor 45 be C. A low pass filter is made up of a resistor 44 and a capacitor 45. This low-pass filter has the same characteristics as the low-pass produced by the monitor photodiode 2 and the 1→V conversion amplifier circuit, and has a cutoff frequency IPc.

FC=1/(2πCR3) となる、演算増幅器48と抵抗46・47で非反転増幅
回路が作られていて、その利得Gは。
A non-inverting amplifier circuit is made up of an operational amplifier 48 and resistors 46 and 47, where FC=1/(2πCR3), and its gain G is.

G=l+R5/R4 となる、第5図に各部の波形を示す1図中、信号49が
基準電圧発生回路2の出力である。記録信号13がm 
H’* o トき、信号49UVlとナリ。
G=l+R5/R4 In FIG. 5, which shows the waveforms of each part, the signal 49 is the output of the reference voltage generation circuit 2. The recording signal 13 is m
H'* o Toki, signal 49UVl and nari.

記録信号13が’ L ” の#、 () N D レ
ヘ、II/ トナル。
Recording signal 13 is 'L'#, ()ND, II/tonal.

加算回路4は演算増幅器等で構成されるもので、信号4
9と電圧源(電圧は72)55を加算する。
The adder circuit 4 is composed of an operational amplifier, etc., and the signal 4
9 and the voltage source (voltage is 72) 55 are added.

その結果、加算回路4の出力40に第5図に示すように
なる。
As a result, the output 40 of the adder circuit 4 becomes as shown in FIG.

この信号40が半導体レーザの光出力を決定する基準電
圧であり、光出力モニタ信号18と差動増幅回路5で差
をとり、ローパスフィルタ28を通してバイアス電流駆
動回路へ入力される。パルス電流駆動回路部分は従来列
で説明したとおシなので、説明を省略する。
This signal 40 is a reference voltage that determines the optical output of the semiconductor laser, and the difference between the signal 40 and the optical output monitor signal 18 is taken by the differential amplifier circuit 5 and is inputted to the bias current drive circuit through the low-pass filter 28. The pulse current drive circuit portion is the same as that described in the conventional column, so a description thereof will be omitted.

第6図に各部の信号波形を示す、リード信号17、イレ
ーズ信号14.記録信号13が図に示すように変化する
と、基準電圧40が得られる。
FIG. 6 shows the signal waveforms of each part, read signal 17, erase signal 14. When the recording signal 13 changes as shown in the figure, a reference voltage 40 is obtained.

第7図に本発明の消去電流駆動回路部分の他の実施例を
示す、この回路は電流加算方式であシ。
FIG. 7 shows another embodiment of the erase current drive circuit portion of the present invention. This circuit is of a current addition type.

電圧源60・スイッチ61−抵抗63・トランジスタ6
4・からなる消去電流駆動回路により半導体レーザ1に
バイアス電流に加算する形で電流を駆動する。ここで、
スイッチ61はイレーズ信号1.5が’ IJ’(0時
1d’l c cK、” H”ORF!’に圧11!1
60に接続されイレーズ時は半導体レーザ1に電流を供
給する。
Voltage source 60, switch 61-resistance 63, transistor 6
An erase current drive circuit consisting of 4. drives a current to the semiconductor laser 1 in a form that is added to the bias current. here,
The switch 61 has the erase signal 1.5 set to 'IJ' (0 o'clock 1d'l c cK, 'H'ORF!' to the pressure 11!1).
60 and supplies current to the semiconductor laser 1 during erasing.

〔発明の効果〕〔Effect of the invention〕

以と述べたように1本発明によれば以下に述べるような
効果がもたらされる1手導体レーザの動作を再生状態か
ら消去状態へまたはその逆に変化させる時に、バイアス
電流に加算する形で消去電流を駆動する消去電流駆動回
路を設けたため、半導体レーザの駆動電流がなまらない
ので、消去すべき領域の最初の部分が消えのこってしま
ったり。
As described above, according to the present invention, when changing the operation of a single-handed conductor laser that brings about the following effects from the reproducing state to the erasing state or vice versa, erasing is performed by adding it to the bias current. Since we provided an erase current drive circuit to drive the current, the drive current of the semiconductor laser does not become dull, so the first part of the area to be erased is sometimes erased.

消去してはいけない領ti!l!e消去してしまうとい
う事がなく、正確に消去できる。さらに本発明はバイア
ス電流駆動回路、消去電流駆動回路、パルス電流駆動回
路をそれぞれ設けたために、再生−記録・消去時の半導
体レーザの光出力を、それぞれ独立に制御できる。
Territory that must not be erased! l! e There is no possibility of erasure, and the data can be erased accurately. Furthermore, since the present invention includes a bias current drive circuit, an erase current drive circuit, and a pulse current drive circuit, the optical output of the semiconductor laser during reproduction, recording, and erasing can be controlled independently.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は1本発明の半導体レーザ駆動回路のブロック図
。 第2図は、従来の半導体レーザ駆動回路図。 第3図は、各部信号波形図。 第4因は、尿発明の一実施例の半導体レーザ駆動回路図
。 第5図は、実施例の各部信号波形図。 第6図は、実施列の各部信号波形図。 第7図は、本発明の他の実施列の主要部分の回路図。 1・・・半導体レーザ 2・・・モニタホトダイオード 3・・・l→V変換増幅回路 4・・拳加算回路 5・・−差動増幅回路 6・・・バイアス電流駆動回路 7・・・消去電流駆動回路 8・・・パルス電流駆動回路 以   と
FIG. 1 is a block diagram of a semiconductor laser drive circuit according to the present invention. FIG. 2 is a conventional semiconductor laser drive circuit diagram. FIG. 3 is a diagram of signal waveforms at each part. The fourth factor is a semiconductor laser drive circuit diagram of an embodiment of the urine invention. FIG. 5 is a signal waveform diagram of each part of the embodiment. FIG. 6 is a signal waveform diagram of each part of the implementation column. FIG. 7 is a circuit diagram of the main parts of another embodiment of the present invention. 1...Semiconductor laser 2...Monitor photodiode 3...L→V conversion amplifier circuit 4...Fist addition circuit 5...-Differential amplifier circuit 6...Bias current drive circuit 7...Erasing current Drive circuit 8...Pulse current drive circuit and more

Claims (1)

【特許請求の範囲】 a)半導体レーザにより記録、再生及び消去を行う光学
式記録再生装置の半導体レーザ駆動回路において、 b)記録信号によりパルス電流を半導体レーザに印加す
る、パルス電流駆動回路と、 c)消去時に半導体レーザに電流を供給する、消去電流
駆動回路と、 d)半導体レーザの光出力をモニタするモニタホトダイ
オードからの電流信号を電圧値に変換増幅する、I→V
変換増幅回路と、 e)再生時の半導体レーザの光出力を設定するための電
圧を発生する、基準電圧発生回路1と、 f)前記記録信号により記録時の半導体レーザの光出力
を設定するための電圧を発生する、基準電圧発生回路2
と、 g)消去時の半導体レーザの光出力を設定するための電
圧を発生する、基準電圧発生回路3と、 h)前記基準電圧発生回路1と、前記基準電圧発生回路
2と、前記基準電圧発生回路3からの出力を加算する加
算回路と、 i)前記I→V変換増幅回路の出力と、前記加算回路の
出力の差をとる差動増幅回路と、j)前記差動増幅回路
からの出力により、半導体レーザにバイアス電流を供給
するバイアス電流駆動回路からなることを特徴とする半
導体レーザ駆動回路。
[Scope of Claims] a) A semiconductor laser drive circuit for an optical recording and reproducing device that performs recording, playback, and erasing using a semiconductor laser, and b) a pulse current drive circuit that applies a pulse current to the semiconductor laser in response to a recording signal; c) an erase current drive circuit that supplies current to the semiconductor laser during erasing, and d) an I→V circuit that converts and amplifies the current signal from the monitor photodiode that monitors the optical output of the semiconductor laser into a voltage value.
a conversion amplifier circuit; e) a reference voltage generation circuit 1 for generating a voltage for setting the optical output of the semiconductor laser during reproduction; and f) for setting the optical output of the semiconductor laser during recording using the recording signal. Reference voltage generation circuit 2 that generates a voltage of
and g) a reference voltage generation circuit 3 that generates a voltage for setting the optical output of the semiconductor laser during erasing; h) the reference voltage generation circuit 1, the reference voltage generation circuit 2, and the reference voltage an adder circuit that adds the outputs from the generator circuit 3; i) a differential amplifier circuit that takes the difference between the output of the I→V conversion amplifier circuit and the output of the adder circuit; and j) the output from the differential amplifier circuit. A semiconductor laser drive circuit comprising a bias current drive circuit that supplies a bias current to a semiconductor laser by its output.
JP61263271A 1986-11-05 1986-11-05 Semiconductor laser driving circuit Pending JPS63117333A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61263271A JPS63117333A (en) 1986-11-05 1986-11-05 Semiconductor laser driving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61263271A JPS63117333A (en) 1986-11-05 1986-11-05 Semiconductor laser driving circuit

Publications (1)

Publication Number Publication Date
JPS63117333A true JPS63117333A (en) 1988-05-21

Family

ID=17387140

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61263271A Pending JPS63117333A (en) 1986-11-05 1986-11-05 Semiconductor laser driving circuit

Country Status (1)

Country Link
JP (1) JPS63117333A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6482682A (en) * 1987-09-25 1989-03-28 Toshiba Corp Semiconductor laser driver

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6482682A (en) * 1987-09-25 1989-03-28 Toshiba Corp Semiconductor laser driver

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