JPS63117130U - - Google Patents
Info
- Publication number
- JPS63117130U JPS63117130U JP845787U JP845787U JPS63117130U JP S63117130 U JPS63117130 U JP S63117130U JP 845787 U JP845787 U JP 845787U JP 845787 U JP845787 U JP 845787U JP S63117130 U JPS63117130 U JP S63117130U
- Authority
- JP
- Japan
- Prior art keywords
- flop
- flip
- clock
- signal
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims description 5
- 230000004069 differentiation Effects 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Time-Division Multiplex Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP845787U JPS63117130U (fi) | 1987-01-23 | 1987-01-23 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP845787U JPS63117130U (fi) | 1987-01-23 | 1987-01-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63117130U true JPS63117130U (fi) | 1988-07-28 |
Family
ID=30792851
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP845787U Pending JPS63117130U (fi) | 1987-01-23 | 1987-01-23 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63117130U (fi) |
-
1987
- 1987-01-23 JP JP845787U patent/JPS63117130U/ja active Pending
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