JPS63116439A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPS63116439A JPS63116439A JP26238786A JP26238786A JPS63116439A JP S63116439 A JPS63116439 A JP S63116439A JP 26238786 A JP26238786 A JP 26238786A JP 26238786 A JP26238786 A JP 26238786A JP S63116439 A JPS63116439 A JP S63116439A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- bonding pad
- integrated circuit
- semiconductor integrated
- prevented
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 230000002159 abnormal effect Effects 0.000 abstract description 2
- 239000011347 resin Substances 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 238000003763 carbonization Methods 0.000 description 1
- 238000002788 crimping Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野〕
この発明は、半導体集積回路、特に半導体集積回路のチ
ップ上に設けられるボンディングパッドに関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor integrated circuit, and particularly to a bonding pad provided on a chip of a semiconductor integrated circuit.
（従来の技術）
第２図は、従来のこの種のチップ上に設けられたワイヤ
ーボンドの一例を示す半導体集積回路の正面図である。(Prior Art) FIG. 2 is a front view of a semiconductor integrated circuit showing an example of a wire bond provided on a conventional chip of this type.
図中、１はチップ、２は、チップ１の周辺部に配設され
ているボンディングパッド、２ａはボンディングパッド
２のうち、電圧供給を目的とするボンディングパッド、
３は、例えば金線より成るワイヤ、３ａは、ボンディン
グパッド２ａ接続用ワイヤ、４はリードフレーム、４ａ
はボンディングパッド２ａと接続しているリードフレー
ム、５はダイパッドフレームである。In the figure, 1 is a chip, 2 is a bonding pad disposed around the chip 1, 2a is a bonding pad among the bonding pads 2 for the purpose of voltage supply,
3 is a wire made of, for example, a gold wire, 3a is a wire for connecting the bonding pad 2a, 4 is a lead frame, 4a
5 is a lead frame connected to the bonding pad 2a, and 5 is a die pad frame.
ワイヤ３は、チップ１とリードフレーム４を接続してい
る。チップ１上にワイヤ３を圧着する場所として設けら
れるボンディングパッド２は、通常、チップ１の周辺部
に必要数設けられるのが一般的である、このボンディン
グパッド２中には、電圧供給を目的とするボンディング
パッド２ａも含まれている。一般的に、ボンディングパ
ッド２ａには、パッド２に比して大電流が流れ、チッ
゛熱遮断回路（図示せず）により、過熱保護を行
っている。′
〔発明が解決しようとする問題点〕
しかしながら、何らかの原因で、前記の熱遮断回路が動
作しないで、過電流がポンディングバッド２ａからダイ
パッドフレーム５に流れた場合、ボンディングパッド２
ａの部分のチップが過電流のために局部的に高温となり
、ダイパッドフレーム５とリードフレーム４８間の樹脂
が炭化し、両フレーム４ａと５が低抵抗で接続された状
態となる可能性があるという問題点があった。Wire 3 connects chip 1 and lead frame 4. The required number of bonding pads 2, which are provided as places for crimping wires 3 on the chip 1, are usually provided around the periphery of the chip 1. Also included is a bonding pad 2a. Generally, a larger current flows through bonding pad 2a than through pad 2, and the chip
``A thermal cutoff circuit (not shown) provides overheat protection. [Problems to be Solved by the Invention] However, if for some reason the heat cutoff circuit does not operate and overcurrent flows from the bonding pad 2a to the die pad frame 5, the bonding pad 2a
There is a possibility that the chip in part a becomes locally high temperature due to overcurrent, and the resin between die pad frame 5 and lead frame 48 is carbonized, resulting in a state in which both frames 4a and 5 are connected with low resistance. There was a problem.
この発明は、上記のような従来例の問題点を解ン肖する
ためになされたもので、両フレーム４ａ。This invention was made in order to solve the problems of the conventional example as described above, and both frames 4a.
５間が樹脂の炭化により電気的に接続されないようにす
ることを目的とする。The purpose is to prevent electrical connection between the parts 5 and 5 due to carbonization of the resin.
このため、この発明に係る半導体集積回路は、チップ上
に設けた電圧供給用ボンディングパッドのみを、チップ
周辺部に設けないようにすることにより、前記目的を達
成しようとするものである。Therefore, the semiconductor integrated circuit according to the present invention attempts to achieve the above object by eliminating only the voltage supply bonding pads provided on the chip from being provided on the periphery of the chip.
（作用）
以上のような手段により、通電流のため、チップ周辺部
が局部的に高温になることなく、電圧供給を目的とする
ボンディングパッド部からの発熱が広い面積に放散され
る。(Function) With the means described above, the heat generated from the bonding pad portion intended for supplying voltage is dissipated over a wide area without causing the peripheral portion of the chip to locally become high in temperature due to current flow.
以下、この発明の実施例を図に基づいて説明する。 Embodiments of the present invention will be described below based on the drawings.
第１図は、この発明の一実施例である半導体集積°回路
の正面図である。第１図は、前出従来例第２図の相当図
で、第２図におけると同一または相当構成要素は同一記
号で表わし、重複説明は省略する。FIG. 1 is a front view of a semiconductor integrated circuit which is an embodiment of the present invention. FIG. 1 is a diagram corresponding to FIG. 2 of the prior art example described above, and the same or equivalent components as in FIG. 2 are represented by the same symbols, and redundant explanation will be omitted.
（構成）
この実施例においては、電圧を供給するワイヤ３ａをチ
ップ１上に圧着するボンディングパッド２ａをチップ１
の周辺部に設けないで、例えばチップ１の中央部近傍に
設けたことを特徴としている。(Structure) In this embodiment, the bonding pad 2a for pressure-bonding the voltage supply wire 3a onto the chip 1 is attached to the chip 1.
It is characterized in that it is not provided at the periphery of the chip 1, but is provided near the center of the chip 1, for example.
〈作用）
この実施例においては、ボンディングパッド２ａをチッ
プ１の中央部近傍に設けているため、ボンディングパッ
ド２ａに仮に異状電流が流れても、熱放散がチップの広
範囲に拡散して行われ、従来例のように、温度上昇が、
チップｌの周辺の局部に集中することがないため、樹脂
が炭化するほどの温度上昇になりにくいので、ダイパッ
ドフレーム５とワードフレーム４ａ間の樹脂が炭化する
ことなく、両フレーム４ａ、５間が電気的に導通となる
ことを防止し得る。<Function> In this embodiment, since the bonding pad 2a is provided near the center of the chip 1, even if an abnormal current flows through the bonding pad 2a, heat is dissipated over a wide area of the chip. As in the conventional example, the temperature rise
Since the temperature is not concentrated in the local area around the chip l, the temperature does not easily rise to the extent that the resin is carbonized, so the resin between the die pad frame 5 and the word frame 4a does not carbonize, and the temperature between the frames 4a and 5 increases. Electrical conduction can be prevented.
以上、説明したように、この発明によれば、電圧供給を
目的とするボンディングパッドをチップの周辺部に設け
ていないので、前記ボンディングパッドに過電流が流九
た場合でも、継続して過電流が流れることを防ぐことが
できる。As explained above, according to the present invention, bonding pads for the purpose of supplying voltage are not provided in the periphery of the chip, so even if an overcurrent flows through the bonding pad, the overcurrent will continue to flow. can be prevented from flowing.
第１図はこの発明の一実施例である半導体集積回路の正
面図
第２図は従来例の一例である半導体集積回路の正面図
１−−−−−−チップ
２ 、 ２ ａ−＝ボンディングパッド３．３ａ軸・・
・・ワイヤFIG. 1 is a front view of a semiconductor integrated circuit which is an embodiment of the present invention. FIG. 2 is a front view of a semiconductor integrated circuit which is an example of a conventional example. 3.3a axis...
・・Wire
Claims (1)
有する半導体集積回路において、電圧供給を目的とする
ボンディングパッドのみを前記周辺部に設けないことを
特徴とする半導体集積回路。1. A semiconductor integrated circuit having a chip in which bonding pads are provided in a peripheral portion of the chip, characterized in that bonding pads for the purpose of supplying voltage are not provided in the peripheral portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26238786A JPS63116439A (en) | 1986-11-04 | 1986-11-04 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP26238786A JPS63116439A (en) | 1986-11-04 | 1986-11-04 | Semiconductor integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63116439A true JPS63116439A (en) | 1988-05-20 |
Family
ID=17375051
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP26238786A Pending JPS63116439A (en) | 1986-11-04 | 1986-11-04 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63116439A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7495684B2 (en) | 2005-01-04 | 2009-02-24 | Funai Electric Co., Ltd. | Printer |
-
1986
- 1986-11-04 JP JP26238786A patent/JPS63116439A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7495684B2 (en) | 2005-01-04 | 2009-02-24 | Funai Electric Co., Ltd. | Printer |
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