JPS63115421A - Oscillation circuit - Google Patents

Oscillation circuit

Info

Publication number
JPS63115421A
JPS63115421A JP26161886A JP26161886A JPS63115421A JP S63115421 A JPS63115421 A JP S63115421A JP 26161886 A JP26161886 A JP 26161886A JP 26161886 A JP26161886 A JP 26161886A JP S63115421 A JPS63115421 A JP S63115421A
Authority
JP
Japan
Prior art keywords
circuit
oscillation
control signal
gate
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26161886A
Other languages
Japanese (ja)
Inventor
Kazuo Aoki
一夫 青木
Hiroshi Kobayashi
洋 小林
Shinji Suda
須田 眞二
Takeshi Shibazaki
柴崎 武
Kenji Arisaka
有坂 研司
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP26161886A priority Critical patent/JPS63115421A/en
Publication of JPS63115421A publication Critical patent/JPS63115421A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To surely stop oscillations synchronously with a control signal by adding an N channel MOS transistor which connected between two terminals of a resonance circuit and has gate input of a control signal for start/stop of oscillations to a position between a drain and a source. CONSTITUTION:A control signal is set at an H level in order to stop oscillations of an oscillation circuit. The output of a 2-input NOR gate 9 forming an amplifying circuit 1 is fixed at an L level. The electric charge stored in a capacitor 8 is discharged in a short time through an output transistor TR set at the L side of the gate 9. In this case, an n channel MOS TR10 connected to both ends of a resonance circuit 5 is turned on and therefore the electric charge stored in a capacitor 7 and an inductance 6 are also discharged in a short time through the TR10 and the output TR set at the L side of the gate 9. As a result, the oscillations of this circuit are surely stopped synchronously with the control signal.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、デジタルIC等に内蔵し、基準信号等を得
るために用いる発振回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an oscillation circuit built into a digital IC or the like and used to obtain a reference signal or the like.

(従来の技術〕 第4図は発振回路の原理を示す回路図であり、1は増幅
回路・、2は帰還回路である。
(Prior Art) FIG. 4 is a circuit diagram showing the principle of an oscillation circuit, where 1 is an amplifier circuit and 2 is a feedback circuit.

また、第5図は実際に使われている発振回路の一例を示
す図であり、1は増幅回路、3はインバータ、4は抵抗
である。5は共振回路であり、第4図の帰還回路2に相
当する。ここで、共振回路5は、例えばこの図の様に、
インダクタンス6、キャパシタ7.8で構成される。
Further, FIG. 5 is a diagram showing an example of an oscillation circuit that is actually used, in which 1 is an amplifier circuit, 3 is an inverter, and 4 is a resistor. 5 is a resonant circuit, which corresponds to the feedback circuit 2 in FIG. Here, the resonant circuit 5 is, for example, as shown in this figure.
It is composed of an inductance of 6 and a capacitor of 7.8.

さらに、第6図は発振回路の他の例を示す図であり、第
5図におけるインバータ3が、2人力NORゲート9に
置き替わったものである。
Furthermore, FIG. 6 is a diagram showing another example of the oscillation circuit, in which the inverter 3 in FIG. 5 is replaced with a two-manpower NOR gate 9.

第4図において、回路が発振するための条件は、増幅回
路1の増幅率をA、帰還回路2の係数をβとすれば、 IA・β1≧1    −・ −・−−−−−(1)L
(A−β)=2ni  (nは整数’)  −(2)で
ある。
In Fig. 4, the conditions for the circuit to oscillate are as follows: If the amplification factor of the amplifier circuit 1 is A, and the coefficient of the feedback circuit 2 is β, then IA・β1≧1 −・−・−−−−−(1 )L
(A-β)=2ni (n is an integer') - (2).

第5図において、上記条件式(11,(2)を最も満足
し易い周波数は 搬用波数となる。すなわち、電源投入等により、回路内
に発生したノイズの中で、(3)式の周波数を持つノイ
ズのみ共振回路5及び増幅回路lが選択的に増幅し、発
振に至るわけである。
In Fig. 5, the frequency that most easily satisfies the above conditional expressions (11, (2)) is the carrier wave number.In other words, the frequency of equation (3) among the noise generated in the circuit by turning on the power, etc. The resonance circuit 5 and the amplifier circuit 1 selectively amplify only the noise that is present, resulting in oscillation.

さて、第5図の回路が発振する際、発振のもとになる信
号はノイズであり、従って、発振開始時の発振出力は“
L”レベルから出力されるのか、″H″レベルから出力
されるのか不定となる。そこで、第6図の様に、インバ
ータ3を2人力N。
Now, when the circuit in Figure 5 oscillates, the signal that causes the oscillation is noise, so the oscillation output at the start of oscillation is "
It is unclear whether the output will be from the L" level or the "H" level. Therefore, as shown in FIG. 6, the inverter 3 is operated by two people.

R9に替え、一方の入力に制御信号を与えると、この回
路はその制御信号が“L”になった時のみ発振し、発振
開始は常に“H”レベルから出力されることになる。こ
の様にしたことで、この発振回路の発振開始を制御信号
に同期をとることができる。
If a control signal is applied to one input instead of R9, this circuit will oscillate only when the control signal becomes "L", and the oscillation will always start from the "H" level. By doing this, the start of oscillation of this oscillation circuit can be synchronized with the control signal.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、第6図に示す従来の発振回路では、発振開始の
同期をとることはできるが、発振停止時正確に同期をと
ることができない。すなわち、共振回路がインダクタン
ス、及びキャパシタで構成されているので、発振時これ
らに蓄積された電荷を、増幅回路(この場合は2人力N
ORゲート)の出力を制御信号によって“H”レベルに
固定し、放電させようとしても、増幅回路の入力側の端
子のキャパシタの電荷がすぐには放電せず、その間発振
を続ける場合がある。また、再び発振を開始させようと
制御信号を入力した時、前回の余振がまだ続いていれば
、発振開始時の出力レベルはその余振の影響を受け、′
L”、“H”どちらから出力されるか不定となる場合が
あるなどの問題点があった。
However, in the conventional oscillation circuit shown in FIG. 6, although it is possible to synchronize the start of oscillation, it is not possible to accurately synchronize when the oscillation is stopped. In other words, since the resonant circuit is composed of an inductance and a capacitor, the charge accumulated in these during oscillation is transferred to an amplifier circuit (in this case, two-man power N
Even if the output of the OR gate is fixed at the "H" level by a control signal and an attempt is made to discharge it, the charge in the capacitor at the input terminal of the amplifier circuit may not be discharged immediately, and oscillation may continue during that time. Also, when a control signal is input to start oscillation again, if the previous aftershock is still continuing, the output level at the start of oscillation will be affected by the aftershock,
There are problems in that it may become unclear whether the output is from "L" or "H".

この発明は上記のような問題点を解消するためになされ
たもので、常に制御信号に同期して発振停止が確実に行
なえる発振回路を得ることを目的とする。
The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide an oscillation circuit that can always reliably stop oscillation in synchronization with a control signal.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る発振回路は、そのドレイン・ソース間を
共振回路の2端子間に接続し、発振開始・停止のための
制御信号をゲート入力とするNチャネルMOS)ランリ
スタを設けたものである。
The oscillation circuit according to the present invention is provided with an N-channel MOS (MOS) run lister whose drain and source are connected between two terminals of a resonant circuit and whose gate is input with a control signal for starting and stopping oscillation.

〔作用〕[Effect]

この発明におけるNチャネルMO3I−ランリスタは、
発振停止時の“H”レベルの制御信号によりONL、共
振回路の人、出力両端を同時に“L″レベル固定し、共
振回路内に蓄積された電荷を短時間に放電させる。
The N-channel MO3I-run lister in this invention is:
When the oscillation is stopped, the control signal at the "H" level fixes the ONL, the resonant circuit, and both ends of the output at the "L" level at the same time, and the charges accumulated in the resonant circuit are discharged in a short time.

〔実施例〕〔Example〕

以下、この発明の一実施例を第1図について説明する。 An embodiment of the present invention will be described below with reference to FIG.

図において、1は増幅回路であり、9はこの増幅回路1
を構成する2人力NORゲート、4は抵抗である。また
5は共振回路であり、6はこの共振回路5を構成するイ
ンダクタンス、7゜8はキャパシタである。さらに、1
0は共振回路5の2端子間に接続されたNチャネルMO
S)ランリスタである。このMOS)ランリスタ10の
ゲートには2人力N0R9の1入力端子に入力される制
御信号が入力される。
In the figure, 1 is an amplifier circuit, and 9 is this amplifier circuit 1.
is a two-man powered NOR gate, and 4 is a resistor. Further, 5 is a resonant circuit, 6 is an inductance constituting this resonant circuit 5, and 7.8 is a capacitor. Furthermore, 1
0 is an N-channel MO connected between two terminals of the resonant circuit 5
S) It is a run lister. A control signal input to one input terminal of the two-man power N0R9 is input to the gate of this MOS) run lister 10.

次に動作について説明する。Next, the operation will be explained.

発振回路の発振を停止させるために、制御信号を“H”
レベルにする。すると、増幅回路1を構成する2人力N
ORゲート9の出力は“L”レベルに固定される。キャ
パシタ8に蓄積された電荷は、この2人力N0R9の6
L″側の出力トランジスタを通じ、短時間に放電される
。そしてこの時、共振回路5の両端に接続されたNチャ
ネルMOS)ランリスタ10がONするので、キャパシ
タ7及びインダクタンス6に蓄積された電荷もこのNチ
ャネルトランジスタ10及び2人力N0R9の“L”側
の出力トランジスタを通して短時間に放電される。すな
わち、共振回路5内に蓄積されている電荷は、制御信号
が“H”レベルになると同時にすべて短時間に放電され
ることになる。
In order to stop the oscillation circuit, the control signal is set to “H”.
level. Then, the two-person power N that makes up the amplifier circuit 1
The output of OR gate 9 is fixed at "L" level. The charge accumulated in the capacitor 8 is 6 of these two people N0R9
It is discharged in a short time through the output transistor on the L'' side.At this time, the N-channel MOS (N-channel MOS) run resistor 10 connected to both ends of the resonant circuit 5 is turned on, so that the charge accumulated in the capacitor 7 and the inductance 6 is also discharged. It is discharged in a short time through this N-channel transistor 10 and the "L" side output transistor of the two-channel N0R9.In other words, the charge accumulated in the resonant circuit 5 is completely discharged as soon as the control signal becomes "H" level. It will be discharged in a short time.

この時、2人力N0R9とNチャネルMOS)ランリス
タ10のサイズを充分大きくしてやれば、発振周期内に
全電荷が放電され、この回路の発振は、制御信号に同期
して、確実に停止する。
At this time, if the sizes of the two-manufactured N0R9 and the N-channel MOS run lister 10 are made sufficiently large, all the charges will be discharged within the oscillation period, and the oscillation of this circuit will surely stop in synchronization with the control signal.

なお、上記実施例では増幅回路lに2人力N0R1段及
び抵抗で構成した回路を用いたが、これは、第2図に示
す様な回路であっても良く、また、帰還回路として、L
6、C7,8からなる共振回路5を用いたが、これも、
第3図に示す様な水晶またはセラミック発振子6aを使
用した共振回路等であっても良く、上記実施例と同様な
効果が得られる。
In the above embodiment, a circuit composed of a two-person N0R stage and a resistor was used for the amplifier circuit l, but this may also be a circuit as shown in FIG.
A resonant circuit 5 consisting of C6, C7, and C8 was used;
A resonant circuit using a crystal or ceramic oscillator 6a as shown in FIG. 3 may be used, and the same effects as in the above embodiment can be obtained.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明に係る発振回路によれば、その
ドレイン・ソース間を共振回路の2端子間に接続し、発
振開始・停止のための制御信号をゲート入力とするNチ
ャネルMO3I−ランリスタを設けたので、制御信号を
“H”レベルにした際共振回路内の蓄積電荷をすべて短
時間に放電でき、非常に簡単な回路構成で発振停止を制
御信号に同期して確実に行なうことができる。
As described above, according to the oscillation circuit according to the present invention, the N-channel MO3I-run lister whose drain and source are connected between two terminals of the resonant circuit and whose gate input is a control signal for starting and stopping oscillation is provided. As a result, when the control signal is set to the "H" level, all accumulated charges in the resonant circuit can be discharged in a short time, and oscillation can be stopped reliably in synchronization with the control signal with a very simple circuit configuration. can.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例による発振回路を示す図、
第2図及び第3図はこの発明の他の実施例による発振回
路の一部を示す図、第4図は発振の原理を示す回路図、
第5図及び第6図は従来の一般的に使用されている発振
回路を示す図である。 1は増幅回路、2は帰還回路、3はインバータ、4は抵
抗、5は共振回路、6はインダクタンス、7.8はキャ
パシタ、9は2人力NORゲート、10はNチャネルM
O3I−ランリスタである。 なお図中同一符号は同−又は相当部分を示す。
FIG. 1 is a diagram showing an oscillation circuit according to an embodiment of the present invention;
2 and 3 are diagrams showing a part of an oscillation circuit according to another embodiment of the present invention, and FIG. 4 is a circuit diagram showing the principle of oscillation,
FIGS. 5 and 6 are diagrams showing conventional and commonly used oscillation circuits. 1 is an amplifier circuit, 2 is a feedback circuit, 3 is an inverter, 4 is a resistor, 5 is a resonant circuit, 6 is an inductance, 7.8 is a capacitor, 9 is a two-power NOR gate, 10 is an N-channel M
O3I-Run Lister. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] (1)発振開始・停止のための制御信号を1つの入力と
する増幅素子を有する増幅回路と、該増幅回路に接続さ
れた共振回路とからなる発振回路において、 そのドレイン・ソース間を上記共振回路の2端子間に接
続し、上記制御信号をゲート入力とするNチャネルMO
Sトランジスタを備えたことを特徴とする発振回路。
(1) In an oscillation circuit consisting of an amplification circuit having an amplification element that receives a control signal for starting and stopping oscillation as one input, and a resonant circuit connected to the amplification circuit, the resonance circuit between the drain and the source N-channel MO connected between two terminals of the circuit and using the above control signal as gate input
An oscillation circuit characterized by comprising an S transistor.
JP26161886A 1986-10-31 1986-10-31 Oscillation circuit Pending JPS63115421A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26161886A JPS63115421A (en) 1986-10-31 1986-10-31 Oscillation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26161886A JPS63115421A (en) 1986-10-31 1986-10-31 Oscillation circuit

Publications (1)

Publication Number Publication Date
JPS63115421A true JPS63115421A (en) 1988-05-20

Family

ID=17364397

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26161886A Pending JPS63115421A (en) 1986-10-31 1986-10-31 Oscillation circuit

Country Status (1)

Country Link
JP (1) JPS63115421A (en)

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