JPS63114371A - Optical writer - Google Patents

Abstract

PURPOSE:To attain versatile picture forming function by providing a picture element density switching means switching picture element density in response to an external picture density command. CONSTITUTION:A write control circuit 11 uses an external picture element density command signal to control the frequency of a picture element synchronizing clock WCLK, the picture element number of a line gate signal LGATE and the picture element number of a frame gate signal FGATE and outputs frequency division information GI1 as an aperture control data and frequency division information DI2 as an optical output data and a reference clock REFM. A light power control circuit 13 gives an optical output signal to a modulation circuit 15 in response to the frequency division information DI2, a picture element density command signal and a detection signal from a laser light monitor sensor provided to a luminous device 1 via a driver 14. The modulation circuit 15 controls the semiconductor laser of the luminous device 1 in response to the video signal VIDEO from the write control circuit 11.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to an optical writing device used in image forming apparatuses and the like.

In general, optical writing devices used in image forming devices such as laser printers, copying machines, and facsimile machines have pixel densities fixed at a constant value, so it is difficult to write images with various pixel densities. The disadvantage is that it cannot be formed.

l-Flag This invention has been made in view of the above points, and an object thereof is to diversify image forming functions.

In order to achieve the above object, the present invention is also provided with a pixel density switching means for switching the pixel density in accordance with an external pixel density command.

Hereinafter, a detailed explanation will be given based on one embodiment of the present invention.

FIG. 1 is a schematic diagram showing an example of an optical writing device embodying the present invention.

In this optical writing device, a laser beam emitted from a light emitter 1 consisting of a semiconductor laser such as a laser diode and a monitoring sensor is incident on a rotating polygon mirror 3 via an aperture 2. The laser beam is turned into a writing beam by the rotation of , and this writing beam is incident on the photoreceptor 5 as a writing surface through the fθ lens 4, thereby forming an electrostatic latent image on the photoreceptor 5 according to the written image. do.

Then, the write control circuit 11 outputs a video signal VIDE in response to write data WDATA etc. sent from the host.
Pixel synchronization clock (pixel clock) WCLK, effective image in the main scanning direction based on the detection signal from the synchronization detection sensor that outputs O and detects the synchronization position as the writing start position in the main scanning direction for write control. Generates and outputs a line gate signal LGATE indicating the area, a frame gate signal FGATE indicating the effective image area in the sub-scanning direction, a line synchronization signal LSYNC as a write start synchronization signal, an erase signal ERASE as a laser beam setting signal outside the write area, etc. In addition, the frequency of the pixel synchronization clock WCLK and the line gate signal LGATE are adjusted in accordance with the pixel density commanded by the pixel density command signal from the host (external).
and the number of pixels of the frame gate signal FGATE, and further outputs frequency division ratio information DII as fringe control data, frequency division ratio information DI2# as optical output data, and a reference clock REFM. In addition.

This write control circuit 11 includes a crystal oscillator 12 for generating a reference clock of frequency F'xT.

The optical power control circuit 13 responds to frequency division ratio information from the write control circuit 11, a pixel density command signal from the host, and a detection signal from a monitor sensor such as a photodiode provided inside the light emitter 1 that receives laser light. driver 14
An optical output signal is provided to the modulation circuit 15 via the modulation circuit 15. The modulation circuit 15 supplies a current to the semiconductor laser of the light emitter 1 according to the optical output signal from the optical power control circuit 13 and turns on/off the semiconductor laser of the light emitter 1 in response to the video signal VIDEO from the write control circuit 11. Off control (modulation control) is performed to cause the light emitter 1 to emit laser light according to the written image.

The PLL control circuit 16 operates the polygon motor 18 via the driver 1 in response to the reference clock REFM from the write control circuit 11, the pixel density command signal from the host, and the feedback signal from the polygon motor 18 that rotationally drives the rotating polygon mirror 3. The rotary polygon mirror 3 is rotated by driving control.

The aperture diameter control circuit 20 drives and controls the aperture motor 22 via a driver 21 in accordance with the division ratio information DII from the write control circuit 11 and the pixel density command signal from the host, thereby controlling the aperture diameter of the embossing device 2. control.

FIG. 2 is a block diagram showing the configuration of the write control circuit 11 of this writing device.

The density converter 30 inputs the pixel density command signal RI from the host, and converts the pixel density command signal RI from the host to a frequency dividing ratio obtained by (RLCM/Ri) based on the least common multiple RLCM of each pixel density and the commanded pixel density Ri. Geometric ratio information (light output information) DI2, least common multiple RLCM of each pixel density, and command pixel density R
Division ratio information DII obtained by (RLcM/R1) based on i and initial value I N I 1s corresponding to 2 pixel density
ync II N I Igate, I N Ier
ase, I N Idsync are output.

The oscillator 31 outputs an image clock CLKN with a frequency F'xT corresponding to the pixel density of the least common multiple RLCM of each pixel density using the crystal resonator 12.

The frequency divider 32 divides the image clock CLKN at the division ratio indicated by the division ratio information input 2 from the density converter 30 and outputs the clock CLKD. The shift register 53 receives the frequency division ratio information 2 from the density converter 30 and generates (DI2) clocks CLKRA-, each of which is phase-shifted from the clock CLKD from the frequency divider 32 by (CLKD/DI2).
Output CLKRD. The latch and data selector 34 shifts a clock that is synchronized with the input phase of the synchronization detection signal DETP, which is a signal obtained by shaping the write light detected by a synchronization detection sensor consisting of a photodetector that inputs laser light before the start of main scanning (not shown). Select from among the clocks CLKRA-CLKRD from the register 33,
Output as pixel clock WCLK.

The synchronization detection counter 35 receives the initial value I N r from the density converter 30 when the synchronization detection signal DETP is input.
dsync is loaded and clock C from divider 31
The count is increased when the count value of LKD reaches the initial value INIdsync. The S-R type flip-flop circuit (hereinafter referred to as rs-R-FF circuit 1) '56 is reset by the synchronization detection signal DETP and is set when the synchronization detection counter 35 counts up, and its Q output is used for data synchronization. Output as signal DSYNC.

The counter 37 is loaded with the initial value lNll5ync from the density converter 30 when the synchronization detection signal DETP is input, counts the pixel clock WCLK from the latch table data selector 34 as a clock input, and connects it to the J-type flip-flop circuit. (hereinafter referred to as "rJ-FF circuit") 38 uses the pixel clock WCLK as a clock input, receives the count value from the counter 37, and outputs a line synchronization signal LSYNC.

When the synchronization detection signal DETP is input, the counter 39 is loaded with the initial value INI1gate from the density converter 30 and counts the pixel clock WCLK from the latch table data selector 34 as a clock input.
The FF circuit 40 receives the count value from the counter 39 using the pixel clock WCLK as a clock input, and outputs a line gate signal LGATE.

The counter 41 is loaded with the initial value INIeraSS from the density converter 30 when the synchronization detection signal DETP is input, counts the pixel clock WCLK from the latch table data selector 34 as a clock input, and outputs it to J-.
The FF circuit 42 receives the count value from the counter 41 using the pixel clock WCLK as a clock input, and outputs an erase signal ERASE. Note that this erase signal ER
ASE is an unnecessary band m (P-P
This is a signal to prevent unnecessary charge removal (N-P method), and here the P-P method is used.

A D-type flip-flop circuit (hereinafter referred to as rD-FF circuit) 43 inputs write data WDATA to its input terminal using the pixel clock WCLK as a clock input. The logical product with the Q output is taken and outputted as the signal WDATA1.

The AND circuit 45 performs a logical product of the erase signal ERASE and a signal obtained by inverting the line gate signal LGATE by the inverter 4B, and outputs the result as an erase signal ERASEI. The OR circuit 47 receives the data synchronization signal DSYNC from the S-R/FF circuit 36 and the signal WDA from the AND circuit 44.
Erase signal ERASE from TE and AND circuit 45
The logical sum is calculated and outputted as a modulation signal VIDEO to the semiconductor laser of the light emitter 1.

The frequency divider 48 inputs the clock CLKN from the oscillator 31 and divides the frequency into a reference clock REFMLCM corresponding to the rotation speed of the rotating polygon mirror 3 when forming an image with a pixel density of the least common multiple RLCM of each pixel density, The frequency divider 49 divides the reference clock REFMLCM from the frequency divider 48 by a frequency division ratio indicated by the frequency division ratio information DII from the density converter 30, and outputs the result as a reference clock REFM.

FIG. 3 is a block circuit diagram showing an example of the optical power control circuit 13 of this writing device.

The up/down counter 51 starts/ends power control by inputting start/stop signals 5TART/5TOP from a controller (not shown) to its enable terminal, and the output of a comparator 64 (to be described later) is at a high level °H.

When the output of the comparator 64 is at the low level °L, the count is counted down.

The D/A converter 52 D/A converts the optical output data, which is the count value of the counter 51, and outputs an analog drawing current signal l0UT. A differential amplifier consisting of an operational amplifier (OF) 53 and a resistor 54 outputs a voltage VOP to the driver 5 according to the difference between the drawing current signal I0IJT from the D/A converter 52 and the reference voltage VREF2. This driver 5 causes a current ILD corresponding to the input voltage VOP to flow into the laser diode 57.

The modulation circuit 58 inputs the modulation signal VIDEO, and at the time of power control, the modulation signal VI is input by a controller (not shown).
Since DEO is set to a high level °H", the output is always set to a high level °H", and the laser diode 57 is in the DC lighting state. During image writing, power control is stopped and the modulation signal VIDEO from the write control circuit 11 is turned on. Adjust the output accordingly.

or °H° to modulate the laser diode 57.

The photodiode 61 receives the light emitted from the laser diode 57 and monitors the light emission output of the laser diode 57. An amplifier including an operational amplifier 62 and a feedback resistor section 63 amplifies the monitor current IM flowing through the photodiode 61 and outputs the amplified monitor current IM to the comparator 64. Comparator 6
4 compares the amplified monitor current IM from the amplifier with the reference voltage VREFz, sets the output to high level °H0 or low level °L° depending on the comparison result, and controls the output of this comparator 64 to the above-mentioned up/down level. It is input to the up/down terminal tJP/DOWN of the counter 51.

Thereby, when the monitor current IM is smaller than the reference value, the current ILD to the laser diode 57 is increased, and when the monitor current IM is larger than the reference value, the current ILD to the laser diode 57 is decreased. , the light emission output PLO of the laser diode 57 is always controlled to be constant.

The feedback resistor section 63 is connected to the laser diode 5 according to the pixel density.
This is a circuit for changing the light emission output PLD of No. 7, and includes resistors RA, 2RA, 4RA, and 8RA.

16RA (The resistance value of each resistor is 2.
4, 8.16 times) connected in series, and an R-2R resistor network consisting of a feedback resistor RLD connected in series, and each resistor RA, 2R
It consists of an analog switch group 67 consisting of analog switches AS, ~AS4 for bypassing A, 4RA, 8RA, and 16RA, and analog switches AS, ~AS4.
is controlled on/off by each of the signals 80 to B4 of frequency division ratio information DI2 from the write control circuit 11, thereby changing the resistance value of the feedback resistor RLD and changing the amplification factor of the monitor current IM.

Although the PLL control circuit 1 is not shown, it is a general PLL control circuit using a reference clock REFM. Although not shown, the fringe diameter control circuit 20 is a general servo motor position control circuit and the R of the optical power control circuit 13 described above.
-2R resistor network and analog switch group.

Next, the operation of this embodiment configured as described above will be explained with reference to FIG. 4 and subsequent figures.

First, the pixel density Rdpi in both the main scanning direction and the sub-scanning direction
(When writing is performed with the writing speed (sub-scanning direction) of the photoconductor 5 as V S U B (inch/5ee) at dat/1nchl, one scanning time T L S Y
NC(see) is TLSYNC=1/ (R-VSUB) (see)
It can be expressed as

Another multi-turn rotation! When the number of surfaces of t3 is NM [pieces] and the focal length of the fθ lens 4 is L F (inch).

The main scanning length LM is LM=4πLF/NM (inch), and therefore the frequency Fw of the pixel clock WCLK is
cLK is FWCLK: (jleLFR')Vsun/Nu(1
/5ee) Furthermore, it is a rotating polygon! The rotation speed FM of I3 is FM
”RVS tJ B/NM (rotation/5e
It can be expressed as c).

Here, the effective image length in the main scanning direction is L main(i
nch), the effective image length in the sub-scanning direction is L 5ub(
If inchl, the number of effective pixels in the main scanning direction N ma
in eThe number of effective images N5ub in the sub-scanning direction is.

Nmain=　RLmain Nsub = RLsub becomes.

Furthermore, the time τLGATE(S
eC] is F'wc L K Similarly, the time τFsyNc (se
e) is τFSYNC=Nsub1TLSYNC=Lsub/V
sub (see).

On the other hand, the beam diameter of the writing light, that is, the aperture D A of the diaphragm 2
P (inchl can be expressed as DA P=KA P/R (inch) (KA p is a constant).

Next, the exposure energy P per unit area on the photoreceptor surface is
s (J/1nch") needs to be constant. In other words, if the diameter of one pixel is I)px, and the energy E of one pixel is the exposure energy per unit time P T (J/5eal), E =
P 7 X 1 / F w CL K. Therefore, PT=FWCLKXsDpX”/4 Here, since DPXO:DAP, D p x =
From K p x / R, P”I’==π”LFVSU
BKPX”/NBJ will remain constant.

Exposure energy P T (J/5ec) on the photoreceptor surface
is constant, but the light emission output PLD of the semiconductor laser (laser diode 57) of the light emitter 1 is PLD (π/4)DLD", where the light emission diameter is DLD, and PLp=R"CDLD/KAP)" PT (J/5ec
) is summarized as 0 or more.

FWCLKa:R" FM=R τLGATE"l/R τF S Y NC=constant DAPO"l/R PLDCI:R" Based on these, the specific contents of each block corresponding to a plurality of pixel densities will be described below.

First, the frequency F'wc LK of one pixel clock WCLK is proportional to the pixel density R (Fwc L x 6cR''), so the least common multiple RLCM of each pixel density R,,R,,R, is RLCM=LCM (Rx s Rx m Rs ), and the oscillation frequency FXT of the crystal resonator 11 is FXT=
4πLFRLCM”°V S tJ B / N H (
1/5ec).

Furthermore, the pixel density of each pixel density R,,R,,R, is 0''/r WCLK frequency F W CL K z + F W
CLK 2 t FW CL Ka is FWCLK
I = FXT/ (RtcM/Rt)”F W CL
K z = F X T / (RL CM / R
s) ”FWCLKi =FXT/ (RLCM/R
3)”, respectively RL CM / Rt (L =
1 , 2 , 3 ) by dividing F'xT with a frequency division ratio of the square of FW CL K L (t = 1
, 2, 3) It is possible to make a production.

Also, the rotational speed FM of the rotating polygon is FM"FWCLK/4πLFR (RLCM/R), where the oscillation frequency FXT of the crystal resonator 11 is (
If the signal frequency-divided by 4gLrRLcu) is FMLCM, then the rotation speed F corresponding to each image density R1, R,, R3
M engineeringtFMz*FMs is F Mx ” F M L
CM/ (RL CM/ Rx) FM! =FMLc
M/ (RLCM/R2)FM! =FMLcM/ [
LCM/Rj).

In other words, from the write control circuit 11, the PLL control circuit 1B
The rotation reference clock REFM for the polygon motor 18 that is output to the polygon motor 18 is obtained by dividing (FXT) in advance at a constant frequency division ratio (4πLrRLCM), and further dividing it by RLCM/gt) corresponding to each pixel density. You can create it by doing so.

Therefore, for example, each pixel density R,,R,,R3゜R4 is set to R,=240dpi and R,=300dpi, respectively.
.

When R, = 400 dpi and R, = 600 dpi, consider a write control circuit 11 that can accommodate these four types of pixel densities. At this time, the least common multiple of each pixel density RL
CM = 1200dpi, and crystal oscillator 1
The oscillation frequency F z 7 of 2 is assumed to be 12 MHz. In addition, as shown in FIG. 4, effective image area Lmain=8' DETP~exposure area=exposure area area 1'=101 DETP NLSYNC=1.5' LSYNC width (k)=8WCLK LSYNCNLGATE (fl)=8WCLKDET
Let P-DSYNC=LM-8=12'. In this case, the above-mentioned parts are as shown in FIG.

Therefore, the timing chart of each part of write control in the main scanning direction when the pixel density R=600 dpi is as shown in FIG.

Therefore, write control in the main scanning direction by the write control circuit 11 will be explained next.

First, the modulation signal VIDEO of the write light is output from the 5-R-FF circuit 36 by the output of the synchronization detection counter 35.
It becomes true when SYNC becomes true, and the write light turns on at this time. In this state, when writing light is incident on a photodetector (not shown), a synchronization detection signal DE is generated.
TP becomes true, and in synchronization with this, the pixel clock WCLK is output from the latch table data selector 34.

At the same time, this synchronization detection signal DETP causes the synchronization detection counter 35 to receive the initial value I N from the density converter 30.
I dsync is loaded and synchronization detection counter 3
5 starts counting again. Further, the 5-R-FF circuit 36 is reset and the signal DSYNC becomes false. As a result of this operation, the modulation signal VIDEO becomes false and the write light is turned off.

In addition, the counter 37 is activated by this synchronization detection signal DETP.
, 39, 41 are initialized, and these counters: 57.
39.41 contains the initial value I N I from the density converter 30
1sync, I N I Igate, I N
I grass.

is loaded and starts counting the pixel clock WCLK.

Then, the erase signal ER from the FF circuit 42 is sent to J-.
After a while after ASE becomes true, a line synchronization signal LSYNC for instructing a data controller (not shown) to start transferring image data WDATA becomes true for a clock period. Note that this line synchronization signal LSYNC is also an image synchronization clock in the sub-scanning direction, and the time τF during which the frame synchronization signal FSYNC is true depends on the pixel density.
The number of line synchronization signals LSYNC within SYNC varies.

After the line synchronization signal LSYNC becomes false, the line gate signal LGATE becomes true with a delay of β clocks. This line gate signal LGATE is a valid image area signal and is true within this area, so that image data from the data controller can be accepted during this period. Therefore, while the line gate signal LGATE is true, the write data WDATA becomes valid and the modulation signal VIDEO changes with the signal WDATA1 synchronized with the pixel clock WCLK. Thereby, the writing light is turned on and off according to the content of the signal WDATAI, and a valid image can be obtained.

Then, for a while after the line gate signal LGATE becomes false, the modulation signal VIDEO remains true due to the erase signal ERASE1.

When this erase signal ERASEI becomes false, the latch table data selector 34 is cleared and the pixel clock W
CLK is turned off, the modulation signal VIDEO becomes false, and the write light is turned off.

After this, the output of the synchronization detection counter 35 becomes true, and the signal D
SYNC becomes true and the modulation signal VIDEO becomes true again. Then, in the first main scanning line where the write light is turned on to perform synchronization detection of the next main scanning line, when the synchronization detection signal DETP is input, the same operation as described above is performed.

Although not shown, the time τFSYNC during which the frame synchronization signal FSYNC is true is constant regardless of the pixel density, so it is clear that the frame synchronization signal FSYNC is easily generated.

During such write control in the main scanning direction, the write control circuit 11 generates a reference clock REFM for determining the rotation speed of the rotating polygon mirror 3 and sends it to the PLL control circuit 1, and this PLL control The circuit 1 drives and controls the polygon motor 18 based on this reference clock REFM. Further, the write control circuit 11 sends frequency division ratio information DI2 to the optical power control circuit 13, and this optical power control circuit 1'5 sends optical output data according to this frequency division ratio information DI2 to the modulation circuit 15. output to control light output. Furthermore,
The frequency division ratio information DII is sent from the write control circuit 11 to the fringe diameter control circuit 20, and the fringe diameter control circuit 20 controls the drive of the motor 22 based on the frequency division ratio information DII to perform the fringe diameter control circuit 20. The beam diameter is controlled by controlling the aperture diameter of the vessel 2.

In other words, the optical power control circuit 13 uses the R-2R resistor network 6 to cope with changes in pixel density as described above.
Monitor current IM with analog switch group 67
The amplification factor of the laser diode 57 can be changed to change the light emission output PLO of the laser diode 57 according to the pixel density.

Here, the least common multiple RLCM of each pixel density R,,R, etc.
If the light emission output required when forming an image is PLDLCM, then the light emission output PLDx*PLDz corresponding to each pixel density R1°R8, etc. is PLD t = P
L D L CM / (RL CM / R1)”
P L D z = P L D L CM / (R
For example, pixel density R = 240 dpi, R.

=300dpi, R,=400dpi, R,=60
Thinking about 0dpi.

R1=240dpi-P LDi = P L D L
CM/25Rz "300dPl"・PLD
z = PL DL CM / 16R, = 400d
pi-PLD3=PLDLCM/9R4=600dpi
・=PLD4=PLDLCM/4.

In other words, it can be seen that the frequency division ratio information DI2 from the write control circuit 11 should be used to control PLD=PLDLCM/DI2.

By the way, in the optical power control circuit 13 of FIG.
The current ILD flowing through the laser diode 57 is ILD=Kt (VREF-VM), and since PLD IM=3・PLD VM"RLD"IM, PLD"KLD/RLD Become. In other words, PLD=PLDLCM/(RLD/RLDLCM)=P
LDLCM/DI2, and RLD"RLDLCM"DI2.

Therefore, the feedback resistance RLD of the operational amplifier 62 is changed to the resistance R
By combining A, 2RA, 4RA, 8RA, and 16RA, appropriate light emission can be achieved by simply turning on (ON)/off (OFF) the analog switches AS0 to AS on analog switch group 6 corresponding to each pixel density. I get the output. The numerical values and operations of each part in this case are as shown in FIG.

The fringe diameter control circuit 20 also controls the fringe diameter DAPti-DA corresponding to the pixel density of the least common multiple RLCM of each pixel density.
If pLcM, the fringe diameter DAP corresponding to each pixel density is
is DAP=DAPLCM-DII, that is, the control of the fringe diameter at each pixel density is D
The rotation angle of the motor 22, which rotates so as to be DII times APLCM, may be position-controlled by θLCM'DII.

In this way, in this optical writing device, the rotation speed of the 9-rotation polygon mirror and the output of the writing light are adjusted according to the pixel density commanded from the outside.

Since it is equipped with a pixel density switching means that switches the pixel density by setting the frequency of the pixel synchronization clock (pixel clock), the number of pixels written in the sub-scanning direction, and the number of pixels written in the main scanning direction to values corresponding to the pixel density, the image forming function is improved. It is possible to aim for diversification.

FIG. 8 is a schematic diagram showing another embodiment of the present invention. Note that parts corresponding to those in FIG. 1 are designated by the same reference numerals, and their explanations will be omitted.

In this embodiment, a pixel density switching knob 72 is provided on the operation panel 71, and characters 71a indicating the pixel density commanded by the switching knob 72 are added. Fix this rod 7
A gaff 5 that meshes with a gear 74 that rotationally drives the print device 2 is fixed to the tip of the rod 73, and a gaff 5 that meshes with a gear 74 that rotationally drives the printing device 2 is fixed to the middle portion of the rod 73 for generating pixel density command information according to the position of the switching knob 72. A rotary switch is installed on the 7th.

Therefore, by rotating the pixel density switching knob 72, the aperture diameter of the crest container 2 is adjusted according to the commanded pixel density, and pixel density command information is written from the rotary switch 76 to the writing control circuit 11. The signal is output to the optical power control circuit 13 and the PLL control circuit 16, and the same control as in the above embodiment is performed.

As explained above, according to the present invention, image forming functions can be diversified.

[Brief explanation of the drawing]

No. 111 is a schematic configuration diagram showing an example of an optical writing device embodying the present invention. FIGS. 2 and 3 are block diagrams of the write control circuit and optical power control circuit. 4 to 7 are explanatory views for explaining the operation thereof, and FIG. 8 is a schematic diagram showing another example of the optical writing device embodying the present invention. 1... Light emitter 2... Diaphragm (aperture) 3... Rotating polygon M4... fθ lens 5... Photoconductor 11... Write control circuit 13... Optical power control circuit 15. ...Modulation circuit 1st day...PLL control circuit 1st day...Polygon motor 20...Finger diameter control circuit 22...Fingerprint remoter 1!4 Figure 5vlJ Figure 7

Claims (1)

[Claims] 1. An optical writing device that emits a light beam according to a written image, characterized in that the optical writing device is equipped with a pixel density switching means that switches the pixel density in accordance with an external pixel density command.