JPS63114225A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63114225A JPS63114225A JP61261180A JP26118086A JPS63114225A JP S63114225 A JPS63114225 A JP S63114225A JP 61261180 A JP61261180 A JP 61261180A JP 26118086 A JP26118086 A JP 26118086A JP S63114225 A JPS63114225 A JP S63114225A
- Authority
- JP
- Japan
- Prior art keywords
- polyimide
- semiconductor chip
- wiring board
- melt
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 229920001721 polyimide Polymers 0.000 claims abstract description 39
- 239000004642 Polyimide Substances 0.000 claims abstract description 38
- 238000000034 method Methods 0.000 claims description 8
- 239000000155 melt Substances 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 2
- 239000000919 ceramic Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000005476 soldering Methods 0.000 description 3
- 230000005260 alpha ray Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000941 radioactive substance Substances 0.000 description 2
- ZSLUVFAKFWKJRC-IGMARMGPSA-N 232Th Chemical compound [232Th] ZSLUVFAKFWKJRC-IGMARMGPSA-N 0.000 description 1
- 229910052776 Thorium Inorganic materials 0.000 description 1
- 229910052770 Uranium Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- JFALSRSLKYAFGM-UHFFFAOYSA-N uranium(0) Chemical compound [U] JFALSRSLKYAFGM-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
Abstract
Description
【発明の詳細な説明】
［概要〕
ポリイミドを融液のままにして、半導体チップと配線基
板とをリード接続し、次いで、ポリイミド融液を固化さ
せる。そうすれば、ポリイミドが両方に接着して、半導
体チップの保持性、伝熱性が改善される。[Detailed Description of the Invention] [Summary] Lead connection is made between a semiconductor chip and a wiring board while the polyimide remains as a melt, and then the polyimide melt is solidified. This will allow the polyimide to adhere to both, improving the retention and heat transfer properties of the semiconductor chip.
［産業上の利用分野］
本発明は半導体装置の製造方法のうち、特に、フェース
ダウンボンディング構造半導体装置の製造方法に関する
。[Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device with a face-down bonding structure.
電子回路においては、その実装密度を高めるために、フ
ェースダウンボンディング構造の半導体装置、例えば、
ビームリード方式やタブ（フィルムキャリヤ）方式の半
導体チップを配線基板またはマザーボード（母基板）に
直接接続する実装構造が知られている。In electronic circuits, in order to increase the packaging density, semiconductor devices with a face-down bonding structure, such as
2. Description of the Related Art Mounting structures are known in which a beam lead type or tab (film carrier) type semiconductor chip is directly connected to a wiring board or a motherboard.
しかし、このような半導体装置は、半導体チップが露出
したままの状態で配線基板に取付けされることが多く、
そきため、基板との密着性について十分な配慮が望まれ
ている。However, such semiconductor devices are often mounted on wiring boards with the semiconductor chip exposed.
Therefore, it is desired that sufficient consideration be given to the adhesion with the substrate.
［従来の技術］
さて、ＩＣやＬＳＩなどの半導体装置においては、高集
積化されるに伴ってソフトエラー（ＳｏｆｔＥｒｒｏｒ
）の問題が表面化してきた。それは、放射性物質からで
るα線によってシリコン中に電子−正孔の対が生じて、
そのために誤動作を起こすことである。このα線は材料
中に含まれるウラニウム（Ｕ）やトリウム（Ｔｈ）から
放出されるもので、パッケージ材料にも含有されている
から十分に留意する必要がある。[Prior Art] As semiconductor devices such as ICs and LSIs become more highly integrated, soft errors occur.
) problems have come to the fore. This is because electron-hole pairs are created in silicon by alpha rays emitted from radioactive substances.
This causes malfunctions. This alpha ray is emitted from uranium (U) and thorium (Th) contained in the material, and is also contained in the package material, so it is necessary to be careful.
従って、通常、半導体装置はこのソフトエラー対策とし
て、半導体チップの表面にポリイミド（１’ｏｌｙｉｍ
ｉｄｅ）を塗布しており、このポリイミドを被覆してお
けば、たとえセラミックパッケージに放射性物質が含ま
れていても、そのポリイミドがα線照射から防護してく
れることが公知となっている。Therefore, as a countermeasure against this soft error, semiconductor devices usually include polyimide (1'olyim) on the surface of the semiconductor chip.
ide), and it is known that if the ceramic package is coated with this polyimide, even if the ceramic package contains a radioactive substance, the polyimide will protect it from alpha ray irradiation.
そのため、フェースダウンボンディング構造の半導体装
置においても、半導体チップの表面にポリイミド（膜厚
５０μｍ程度）を被覆しており、第２図はフェースダウ
ンボンディング構造のうちのビームリード形式の半導体
チップの実装構造の断面図を示している。同図において
、ｌは半導体チップ、２はポリイミド、３は半導体チッ
プに形成したビームリード、４は半田付は部分、５は配
線基板である。配線基板５にはプリント基板やマザーボ
ードなどがあるが、半導体チップの実装密度を高くして
、十分な放熱が要求される場合は、セラミック基板が用
いられ、そのセラミック基板には特にポリイミドの被覆
が必須になる。Therefore, even in semiconductor devices with a face-down bonding structure, the surface of the semiconductor chip is coated with polyimide (film thickness of about 50 μm). Figure 2 shows the mounting structure of a beam lead type semiconductor chip in the face-down bonding structure. shows a cross-sectional view of. In the figure, 1 is a semiconductor chip, 2 is polyimide, 3 is a beam lead formed on the semiconductor chip, 4 is a soldering part, and 5 is a wiring board. The wiring board 5 can be a printed circuit board, a motherboard, etc., but if the mounting density of semiconductor chips is high and sufficient heat dissipation is required, a ceramic board is used, and the ceramic board is particularly coated with polyimide. becomes mandatory.
第３図ｆａｎ、 （ｂ）に第２図のビームリード形式半
導体装置の形成方法の断面図を図示しており、まず、同
図（ａ）に示すように、半導体チップ１の表面にポリイ
ミド２の融液をノズルＮから滴下する。次いで、３５０
〜４００℃に加熱してキュア（固化）させた後、第３図
（ｂ）に示すように、配８＃１基板５にビームリードを
接触して半田付けして、第３図のように仕上げる。FIG. 3(b) shows a cross-sectional view of the method for forming the beam lead type semiconductor device shown in FIG. 2. First, as shown in FIG. Drop the melt from nozzle N. Then 350
After curing (solidifying) by heating to ~400°C, as shown in Fig. 3(b), the beam lead is brought into contact with the #1 board 5 and soldered, as shown in Fig. 3. Finish.
このようにして、フェースダウンボンディング構造の半
導体装置が配線基板に実装されている。In this way, a semiconductor device with a face-down bonding structure is mounted on a wiring board.
［発明が解決しようとする問題点コ
ところが、このような実装構造の半導体装置は、ポリイ
ミドを半導体チップに接着し固化した後、配線基板に半
田付けするために、粘度の高いポリイミドは均一に平坦
化されずに、ポリイミドが配線基板に密着せず、従って
、伝熱効果も良くなく、且つ、半４体チップは接続電極
（上記例ではビームリード）のみで支持されていると云
った問題点がある。。[Problems to be Solved by the Invention] However, in semiconductor devices with such a mounting structure, the polyimide is bonded to the semiconductor chip, solidified, and then soldered to the wiring board. The problem is that the polyimide does not adhere closely to the wiring board, so the heat transfer effect is not good, and the half-quad chip is supported only by the connecting electrodes (beam leads in the above example). There is. .
本発明は、この欠点を除去した半導体装置の製造方法を
提案するものである。The present invention proposes a method for manufacturing a semiconductor device that eliminates this drawback.
［問題点を解決するための手段］
その目的は、流れ止め部を設けた配線基板上に、ポリイ
ミド融液を滴下し、次いで、半導体チップと配線基板と
をリード接続した後、前記ポリイミド融液を固化させて
、前記半導体チップとポリイミドとの両方に接着させる
工程が含まれる半導体装置の製造方法によって達成され
る。[Means for solving the problem] The purpose is to drop a polyimide melt onto a wiring board provided with a flow stopper, and then, after connecting the semiconductor chip and the wiring board with leads, drop the polyimide melt onto a wiring board provided with a flow stopper. This is achieved by a method for manufacturing a semiconductor device that includes the steps of solidifying and adhering to both the semiconductor chip and polyimide.
［作用１
即ち、本発明は、ポリイミドの融液を滴下したままの状
態で半導体チップをマウントし、その後、固化させる。[Operation 1] That is, in the present invention, a semiconductor chip is mounted while the polyimide melt is dropped, and then it is solidified.
そうすれば、半導体チップに対してポリイミドが均一な
厚みに接着し、且つ、半導体チップも確実に保持されて
、伝熱効果も向上する。By doing so, the polyimide adheres to the semiconductor chip with a uniform thickness, the semiconductor chip is also securely held, and the heat transfer effect is also improved.
［実施例〕 以下、図面を参照して実施例によって詳細に説明する。[Example〕 Hereinafter, embodiments will be described in detail with reference to the drawings.
第１図（ａｌ〜（Ｃ１は本発明にかかる形成方法の工程
順断面図を示しており、まず、同図＋ａ）に示すように
、配線基板５の半導体チップｌを取りつける位置にポリ
イミド２の融液をノズルＮから滴下する。FIG. 1 (al~(C1) shows step-by-step cross-sectional views of the forming method according to the present invention. First, as shown in FIG. Drop the melt from nozzle N.
そのため、ポリイミド１２の融液が滴下後に周囲に流れ
て広がらないように、配線基板５のチ・ノブ取付は位置
を凹部状５１に形成しておく。また、凹部状５１の代わ
りに、チップ取付は位置の周囲に凸部を形成してもよく
、これらの凹凸はポリイミドの粘度が高いから、僅かの
厚さく３０μｍ程度）で十分に堰止めの役目を果たす。Therefore, in order to prevent the melt of the polyimide 12 from flowing and spreading around the wiring board 5 after being dropped, the chi-knob mounting position of the wiring board 5 is formed in a concave shape 51. In addition, instead of the concave shape 51, a convex part may be formed around the chip mounting position, and since the viscosity of polyimide is high, these convexities have a small thickness (about 30 μm) and are sufficient to act as a dam. fulfill.
且つ、これらの凹凸は、配線基板５がマザーボートの場
合はセラミック焼成時にパターンニングして作成するこ
とができ、プリント基板の場合は配線パターン作成時に
、同時に作成することができる。In addition, if the wiring board 5 is a motherboard, these unevenness can be created by patterning during ceramic firing, and if it is a printed circuit board, they can be created at the same time as the wiring pattern is created.
次いで、第１図（ｂ）に示すように、半導体チップ１を
ポリイミド２の融液の上に載せる。そして、ビームリー
ドを半田付けした後、３５０〜４００℃に加熱してキュ
アさせて、同図（Ｃ）のように仕上げる。Next, as shown in FIG. 1(b), the semiconductor chip 1 is placed on the melted polyimide 2. After the beam leads are soldered, they are heated to 350 to 400° C. to cure them, resulting in a finish as shown in FIG. 4(C).
そうすれば、半導体チップと配線基板との両方にポリイ
ミドが接着して、ポリイミドの厚みが均一になり、且つ
、そのポリイミドによって半導体チップ１が支持されて
保持が確実になり、且つ、ポリイミドを通じての熱伝導
性も良くなる。By doing so, the polyimide adheres to both the semiconductor chip and the wiring board, the thickness of the polyimide becomes uniform, and the semiconductor chip 1 is supported by the polyimide to ensure secure holding. Thermal conductivity also improves.
更に、リード接続の半田付は作業と連続して、ポリイミ
ドをキュアさせれば、作業工程も簡単になる。Furthermore, the work process can be simplified by curing the polyimide while soldering the lead connections.
上記はビームリード形式の半導体装置の例であるが、タ
ブ方式その他のフェースダウンボンディング構造の半導
体装置にも適用できることは云うまでもない。Although the above is an example of a beam lead type semiconductor device, it goes without saying that the present invention can also be applied to a semiconductor device of a tab type or other face-down bonding structure.
〔発明の効果コ
以上の説明から明らかなように、本発明によれば、ソフ
トエラ一対策用のポリイミドを塗布するフェースダウン
ボンディング構造半導体装置において、ポリイミドの厚
みが均一になり、半導体チップは安定に保持され、且つ
、伝熱効果も良くなって、高信頬化される効果がある。[Effects of the Invention] As is clear from the above description, according to the present invention, in a semiconductor device with a face-down bonding structure in which polyimide is coated to prevent soft errors, the thickness of the polyimide becomes uniform, and the semiconductor chip becomes stable. It is retained and the heat transfer effect is also improved, which has the effect of making it more reliable.
第１図（ａ）〜（Ｃ）は本発明にかかる形成方法の工程
順断面図、
第２図はビームリード形式の半導体装置の断面図、第３
図（ａ）、 （ｂｌは従来の形成方法の工程順断面図で
ある。
図において、
１は半導体チップ、 ２．１２はポリイミド、３は
ビームリード、 ４は半田付け、５は配線基板、
５１は凹部状
を示している。
１−？−４任す７７″
Δ”ＺＢＪ”ｌ＋＝ａ・か）形ベガ壜のニオＹ頭葉ｒ旬
フ第１図
ビームリード′〃すへ・字、４．碧１多ず漬Ｉケ面Ｈ刀
第２図
’Ｌｆ−６つうｙシ賎゛方及ａ＋Ｔｊｉ−ノＷｉｆｒａ
ｎＭｒ第３図1(a) to 1(C) are cross-sectional views in the order of steps of the formation method according to the present invention; FIG. 2 is a cross-sectional view of a beam lead type semiconductor device;
Figures (a) and (bl) are step-by-step cross-sectional views of the conventional forming method. In the figures, 1 is a semiconductor chip, 2.12 is a polyimide, 3 is a beam lead, 4 is soldering, 5 is a wiring board,
51 indicates a concave shape. 1-? -4 leave 77″ Δ”ZBJ”l+=a・ka) shaped Vega bottle nio Y head leaf r junfu figure 1 beam lead'〃suhe・ji, 4. Aoi 1 tazuzuke I kamen H sword Figure 2 'Lf-6 side y side and a+Tji-no Wifra
nMr figure 3
Claims (1)
、流れ止め部を設けた配線基板上に、ポリイミド融液を
滴下し、次いで、半導体チップと配線基板とをリード接
続した後、前記ポリイミド融液を固化させて、前記半導
体チップとポリイミドとの両方に接着させる工程が含ま
れてなることを特徴とする半導体装置の製造方法。In a semiconductor device with a face-down bonding structure, a polyimide melt is dropped onto a wiring board provided with a flow stopper, and then the semiconductor chip and the wiring board are connected by leads, and then the polyimide melt is solidified, A method for manufacturing a semiconductor device, comprising the step of bonding both the semiconductor chip and polyimide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61261180A JPS63114225A (en) | 1986-10-31 | 1986-10-31 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61261180A JPS63114225A (en) | 1986-10-31 | 1986-10-31 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63114225A true JPS63114225A (en) | 1988-05-19 |
Family
ID=17358240
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61261180A Pending JPS63114225A (en) | 1986-10-31 | 1986-10-31 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63114225A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59106140A (en) * | 1982-12-10 | 1984-06-19 | Matsushita Electronics Corp | Semiconductor device |
-
1986
- 1986-10-31 JP JP61261180A patent/JPS63114225A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59106140A (en) * | 1982-12-10 | 1984-06-19 | Matsushita Electronics Corp | Semiconductor device |
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