JPH0555633A - Optical device and its manufacture - Google Patents

Optical device and its manufacture

Info

Publication number
JPH0555633A
JPH0555633A JP21868591A JP21868591A JPH0555633A JP H0555633 A JPH0555633 A JP H0555633A JP 21868591 A JP21868591 A JP 21868591A JP 21868591 A JP21868591 A JP 21868591A JP H0555633 A JPH0555633 A JP H0555633A
Authority
JP
Japan
Prior art keywords
light emitting
emitting element
element array
array chip
flux
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21868591A
Other languages
Japanese (ja)
Inventor
Takeshi Fujiwara
武司 藤原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP21868591A priority Critical patent/JPH0555633A/en
Publication of JPH0555633A publication Critical patent/JPH0555633A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Led Device Packages (AREA)
  • Led Devices (AREA)

Abstract

PURPOSE:To prevent residual flux in a light transmission path from mixing into transparent resin of an optical device. CONSTITUTION:A solder bump 5 with flux 19 applied on an end of a light emitting element array chip 13 is formed, while an anti-tilting stud 6 without flux applied is provided at the opposite end, and transparent resin 20 for protecting the light emitting element array chip 13 and the solder bump 5 is injected from a side of the anti-tilting stud 6.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体基板上に発光
部、半田バンプを有する発光素子アレイチツプを面実装
してなる光学装置およびその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical device in which a light emitting element array chip having a light emitting portion and a solder bump is surface-mounted on a semiconductor substrate, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】図7は従来の光学装置の断面図、図8は
同じくその平面図、図9は同じく発光素子アレイの正面
図、図10は同じくその断面図、図11は同じく光学装
置のリフロー前の状態を示す断面図、図12は同じくそ
のリフローおよび洗浄後の状態を示す断面図である。
2. Description of the Related Art FIG. 7 is a sectional view of a conventional optical device, FIG. 8 is a plan view thereof, FIG. 9 is a front view of a light emitting element array, FIG. 10 is a sectional view of the same, and FIG. FIG. 12 is a sectional view showing a state before reflow, and FIG. 12 is a sectional view showing a state after the reflow and cleaning.

【0003】図9,10において、13は発光素子アレ
イチツプ(LEDアレイチツプ)であり、1は砒化ガリ
ウム(GaAs)等の半導体基板で、窒化シリコン等か
らなる選択拡散マスク兼絶縁被膜1aを形成し、中央部
に拡散用の穿孔部を設け、その穿孔部に拡散方法等によ
りpn接合を形成し、発光部2を構成している。4は給
電用電極でアルミニウム等からなり、発光部2の配列方
向に直交する方向に交互に配置しており、その上に窒化
シリコン等からなる絶縁被膜3が被着されている。この
絶縁被膜3には穿孔部があり、その上に順次バリア層
(図示せず)、メツキ法等による半田バンプ5を形成し
ている。
In FIGS. 9 and 10, 13 is a light emitting element array chip (LED array chip), 1 is a semiconductor substrate of gallium arsenide (GaAs) or the like, and a selective diffusion mask / insulating film 1a made of silicon nitride or the like is formed, A perforated portion for diffusion is provided in the central portion, and a pn junction is formed in the perforated portion by a diffusion method or the like to form the light emitting section 2. Reference numeral 4 denotes a power feeding electrode made of aluminum or the like, which are alternately arranged in a direction orthogonal to the arrangement direction of the light emitting portions 2, and an insulating coating 3 made of silicon nitride or the like is deposited thereon. The insulating coating 3 has a perforated portion, on which a barrier layer (not shown) and solder bumps 5 are sequentially formed by a plating method or the like.

【0004】次に、発光素子アレイチツプ13を実装し
た300DPIの光学装置を、プリントヘツドを例にあ
げて説明する。
Next, a 300 DPI optical device in which the light emitting element array chip 13 is mounted will be described by taking a print head as an example.

【0005】図7〜8の如く、基板8はガラス等の透光
性を有する材料からなり、多数の光フアイバーよりなる
フアイバー束9が埋設されており、その表面には薄膜工
程によりアルミニウムおよび銅等の導体パターン10お
よび共通電極パターン11が形成され、接続部以外は窒
化ケイ素等からなる絶縁被膜12が形成されている。
As shown in FIGS. 7 to 8, the substrate 8 is made of a translucent material such as glass, and a fiber bundle 9 composed of a large number of optical fibers is embedded in the substrate 8. The surface of the fiber bundle 9 is made of aluminum and copper by a thin film process. And the like, and a common electrode pattern 11 are formed, and an insulating coating 12 made of silicon nitride or the like is formed except for the connection portion.

【0006】この導体パターン10上には、発光素子ア
レイチツプ13およびこの発光素子アレイチツプ13を
制御するICチツプ15が半田バンプ5により、それぞ
れ接続されており、発光させるための一方の端子として
働く。なお、発光素子アレイチツプ13の発光部2はフ
アイバー束9と対向するようになつている。
On the conductor pattern 10, a light emitting element array chip 13 and an IC chip 15 for controlling the light emitting element array chip 13 are respectively connected by solder bumps 5 and serve as one terminal for emitting light. The light emitting portion 2 of the light emitting element array chip 13 faces the fiber bundle 9.

【0007】この半田バンプ5の接続方法は、図11の
如く、導体パターン10上にボンダーにて転写法等によ
りフラツクス18を塗布し、その上に発光素子アレイチ
ツプ13およびICチツプ15を搭載する。発光素子ア
レイチツプ13およびICチツプ15は、フラツクス1
8により仮接着され、この状態で、図12の如く、リフ
ロー工程を通すことにより半田バンプ5が熔融し、導体
パターン10と接続される。
In the method of connecting the solder bumps 5, as shown in FIG. 11, a flux 18 is applied on the conductor pattern 10 by a transfer method using a bonder, and the light emitting element array chip 13 and the IC chip 15 are mounted thereon. The light emitting element array chip 13 and the IC chip 15 are
Then, the solder bumps 5 are melted by passing through the reflow process as shown in FIG.

【0008】次に、アセトン、IPA等にてフラツクス
18を洗浄する。
Next, the flux 18 is washed with acetone, IPA or the like.

【0009】基板8と発光素子アレイチツプ13および
ICチツプ15の間には、エポキシ樹脂等の材料からな
る透明樹脂20がデイスペンサー等にて充填されてお
り、発光素子アレイチツプ13、ICチツプ15および
半田バンプ5を保護するとともに、発光素子アレイチツ
プ13の発光部2から発した光を透過してフアイバー束
9を介して感光体上に照射する働きをする。
A transparent resin 20 made of a material such as epoxy resin is filled between the substrate 8 and the light emitting element array chip 13 and the IC chip 15 by a dispenser or the like, and the light emitting element array chip 13, the IC chip 15 and the solder. It protects the bumps 5 and also serves to transmit the light emitted from the light emitting portion 2 of the light emitting element array chip 13 and irradiate it onto the photoconductor through the fiber bundle 9.

【0010】発光素子アレイチツプ裏面の共通信号電極
14は、例えば銀の粉末を混入したエポキシ樹脂等の導
電性樹脂21をデイスペンサー、マスク印刷等にて塗布
することにより共通電極パターン11に接続され、発光
させるための共通電極側端子として働く。
The common signal electrode 14 on the back surface of the light emitting element array chip is connected to the common electrode pattern 11 by applying a conductive resin 21 such as an epoxy resin mixed with silver powder by a dispenser or mask printing. It works as a common electrode side terminal for emitting light.

【0011】300DPIの場合、発光素子アレイチツ
プ13は直線上に40個配列され、発光素子アレイチツ
プ13の発光部2は合計2560個直線上に構成され
る。
In the case of 300 DPI, 40 light emitting element array chips 13 are arranged on a straight line, and a total of 2560 light emitting elements 2 of the light emitting element array chip 13 are arranged on a straight line.

【0012】[0012]

【発明が解決しようとする課題】しかしながら、従来の
方法では発光素子アレイチツプ13をフエイスダウン
(F/D)ボンデイング後、リフロー、洗浄する工程に
おいて両サイドに半田バンプ5があるため、図12の如
く、洗浄液の流れが悪く、中央の発光部2にフラツクス
残渣19が残り、発光部2から発した光の透過の妨げに
なる問題があつた。
However, in the conventional method, the solder bumps 5 are provided on both sides in the steps of reflowing and cleaning after the light emitting element array chip 13 is bonded by face down (F / D) bonding, and therefore, as shown in FIG. However, the flow of the cleaning liquid is poor, and the flux residue 19 remains in the central light emitting unit 2, which impedes the transmission of light emitted from the light emitting unit 2.

【0013】また、透明樹脂20を注入する際に半田バ
ンプ5の周囲に付着したフラツクス残渣19が透明樹脂
20に混入してしまい、同様に光の透過の妨げになる問
題があつた。
Further, when the transparent resin 20 is injected, the flux residue 19 adhering to the periphery of the solder bumps 5 is mixed into the transparent resin 20, which also causes a problem of impeding light transmission.

【0014】本発明は、上記課題に鑑み、透明樹脂注入
後、透明樹脂内の光透過路中のフラツクス残渣を防止し
得る光学装置およびその製造方法の提供を目的とする。
In view of the above problems, it is an object of the present invention to provide an optical device capable of preventing a residue of a flux in a light transmission path in a transparent resin after injecting the transparent resin, and a manufacturing method thereof.

【0015】[0015]

【課題を解決するための手段】本発明請求項1による課
題解決手段は、図1〜6の如く、発光素子アレイチツプ
13からの照射光を基板8を通過させて外部へ照射する
ものであつて、前記発光素子アレイチツプ13が透光性
の基板8上に空隙Xを有して面実装され、空隙X内の前
記発光素子アレイチツプ13の電極4と基板8上の導体
パターン10との間に接続用の半田バンプ5が介在さ
れ、前記空隙Xが透明樹脂20にて封止された光学装置
において、前記電極4は、前記発光素子アレイチツプ1
3の一端部にのみ配置され、該発光素子アレイチツプ1
3の他端部には傾斜防止用の突起6が設けられたもので
ある。
The means for solving the problems according to claim 1 of the present invention is to irradiate the irradiation light from the light emitting element array chip 13 to the outside through the substrate 8 as shown in FIGS. The light emitting element array chip 13 is surface-mounted on the transparent substrate 8 with a gap X, and is connected between the electrode 4 of the light emitting element array chip 13 in the gap X and the conductor pattern 10 on the substrate 8. In the optical device in which the solder bump 5 for soldering is interposed and the gap X is sealed with the transparent resin 20, the electrode 4 is the light emitting element array chip 1
3 is arranged only at one end of the light emitting element array chip 1
The other end of 3 is provided with a protrusion 6 for preventing inclination.

【0016】本発明請求項2による課題解決手段は、発
光素子アレイチツプ13の一端部に電極4を形成し、該
電極4に半田バンプ5を突出形成し、発光素子アレイチ
ツプ13の他端に傾斜防止用の突起6を突出形成し、前
記半田バンプ5にフラツクス18を塗布し、該半田バン
プ5を基板8上の導体パターン10に接触させて仮接続
し、発光素子アレイチツプ13と基板8との間に基板8
を有したまま半田リフローして面実装し、空隙Xの突起
6側から透明樹脂20を注入して空隙Xを樹脂封止する
ものである。
According to a second aspect of the present invention, the electrode means 4 is formed at one end of the light emitting element array chip 13, the solder bumps 5 are projectingly formed on the electrode 4, and the other end of the light emitting element array chip 13 is prevented from tilting. Protrusions 6 are formed on the solder bumps 5, a flux 18 is applied to the solder bumps 5, and the solder bumps 5 are brought into contact with the conductor patterns 10 on the substrate 8 to temporarily connect the solder bumps 5 between the light emitting element array chip 13 and the substrate 8. On board 8
With the above, the solder reflow is performed and the surface mounting is performed, and the transparent resin 20 is injected from the protrusion 6 side of the void X to seal the void X with the resin.

【0017】[0017]

【作用】上記課題解決手段において、半田バンプ5にフ
ラツクス18を塗布し、半田バンプ5を基板8上の導体
パターン10に接触させて仮接続する。この際、突起6
にはフラツクスを塗布しないでおく。次に、発光素子ア
レイチツプ13と基板8との間に基板8を有したまま半
田リフローして面実装する。そして、空隙Xの突起6側
から透明樹脂20を注入して空隙Xを樹脂封止する。
In the above means for solving the problems, the flux 18 is applied to the solder bumps 5, and the solder bumps 5 are brought into contact with the conductor patterns 10 on the substrate 8 to be temporarily connected. At this time, the protrusion 6
Do not apply flux to the. Next, the substrate 8 is held between the light emitting element array chip 13 and the substrate 8 by solder reflow and surface mounting. Then, the transparent resin 20 is injected from the protrusion 6 side of the void X to seal the void X with resin.

【0018】このとき、注入口となる突起6の周辺にフ
ラツクスを塗布しないでいるため、透明樹脂20の注入
時にフラツクスの残渣の混入を防止できる。
At this time, since the flux is not applied around the projection 6 serving as the injection port, it is possible to prevent the residue of the flux from being mixed when the transparent resin 20 is injected.

【0019】[0019]

【実施例】図1は本発明第一実施例の光学装置を示す断
面図、図2は同じくその平面図、図3は同じく発光素子
アレイチツプの正面図、図4は同じくその断面図、図5
は同じく光学装置のリフロー前の状態を示す断面図、図
6は同じくそのリフローおよび洗浄後の状態を示す断面
図である。
1 is a sectional view showing an optical device of a first embodiment of the present invention, FIG. 2 is a plan view thereof, FIG. 3 is a front view of a light emitting element array chip, FIG. 4 is a sectional view thereof, and FIG.
Is a sectional view showing a state before the reflow of the optical device, and FIG. 6 is a sectional view showing a state after the reflow and cleaning similarly.

【0020】図1〜6の如く、本実施例の光学装置は、
LEDプリンタ等に使用され、発光素子アレイチツプ1
3からの照射光を基板8を通過させて外部へ照射するL
EDプリントヘツドであつて、発光素子アレイチツプ1
3が透光性の基板8上に空隙Xを有して面実装され、空
隙X内の前記発光素子アレイチツプ13の電極4と基板
8上の導体パターン10との間に接続用の半田バンプ5
が介在され、前記空隙Xが透明樹脂20にて封止されて
いる。
As shown in FIGS. 1 to 6, the optical device of this embodiment is
Used in LED printers, etc., light emitting element array chip 1
L for irradiating the irradiation light from No. 3 to the outside through the substrate 8
ED print head, light emitting element array chip 1
3 is surface-mounted on the transparent substrate 8 with a gap X, and solder bumps 5 for connection are provided between the electrode 4 of the light emitting element array chip 13 in the gap X and the conductor pattern 10 on the substrate 8.
And the gap X is sealed with the transparent resin 20.

【0021】まず、前記発光素子アレイチツプ13につ
いて説明する。図3,4において、1は砒化ガリウム
(GaAs)等の半導体基板で、窒化シリコン等からな
る選択拡散マスク兼絶縁被膜1aを形成し、中央部に拡
散用の穿孔部を設け、その穿孔部に拡散方法等によりp
n接合を形成し、発光部2を構成している。4は給電用
電極でアルミニウム等からなり、発光部2の配列方向に
直交する方向に交互に配置しており、その上に窒化シリ
コン等からなる絶縁被膜3が被着されている。この絶縁
被膜3の一端部には穿孔部が形成され、その上に順次バ
リア層、メツキ法等による半田バンプ5を形成してい
る。なお、バリア層については省略する。
First, the light emitting element array chip 13 will be described. In FIGS. 3 and 4, reference numeral 1 denotes a semiconductor substrate made of gallium arsenide (GaAs) or the like, on which a selective diffusion mask / insulating film 1a made of silicon nitride or the like is formed, and a perforation portion for diffusion is provided in the central portion, and the perforation portion is provided. P depending on the diffusion method
An n-junction is formed to form the light emitting section 2. Reference numeral 4 denotes a power feeding electrode made of aluminum or the like, which are alternately arranged in a direction orthogonal to the arrangement direction of the light emitting portions 2, and an insulating coating 3 made of silicon nitride or the like is deposited thereon. A perforated portion is formed at one end of the insulating coating 3, and a barrier layer and a solder bump 5 by a plating method or the like are sequentially formed thereon. The barrier layer is omitted.

【0022】また、該発光素子アレイチツプ13の他
端、すなわち半田バンプ5の反対側には、ニツケル、チ
タン等の材料からなるパツド7を形成し、絶縁被膜3を
被着する。この絶縁被膜3に穿孔部を設け、その上に2
〜10個の銅等の材料からなる傾斜防止用突起6(スタ
ツド)をメツキ法等により形成している。
On the other end of the light emitting element array chip 13, that is, on the opposite side of the solder bump 5, a pad 7 made of a material such as nickel or titanium is formed, and an insulating coating 3 is applied thereto. The insulating coating 3 is provided with a perforated portion, and 2 is formed on the perforated portion.
Ten to ten inclination preventing projections 6 (studs) made of a material such as copper are formed by a plating method or the like.

【0023】次に図1,2により、前記発光素子アレイ
チツプ13を実装した300DPIのプリントヘツドに
ついて説明する。
Next, referring to FIGS. 1 and 2, a 300 DPI print head on which the light emitting element array chip 13 is mounted will be described.

【0024】基板8はガラス等の透光性を有する材料か
らなり、多数の光フアイバーよりなるフアイバー束9が
埋設し、その表面には薄膜工程により、アルミニウムお
よび銅等の導体パターン10および共通電極パターン1
1を形成し、接続部以外は窒化ケイ素等からなる絶縁被
膜12を形成している。
The substrate 8 is made of a translucent material such as glass, and a fiber bundle 9 made up of a large number of optical fibers is embedded in the substrate 8. The surface of the substrate bundle 9 is formed by a thin film process by a conductor pattern 10 such as aluminum and copper and a common electrode. Pattern 1
1 is formed, and the insulating coating 12 made of silicon nitride or the like is formed except the connection portion.

【0025】この導体パターン10上には、発光素子ア
レイチツプ13およびこの発光素子アレイチツプ13を
制御するICチツプ15が半田バンプ5によりそれぞれ
接続されており、発光させるための一方の端子として働
く。なお、発光素子アレイチツプ13の発光部2はフア
イバー束9と対向するようになつている。
On the conductor pattern 10, a light emitting element array chip 13 and an IC chip 15 for controlling the light emitting element array chip 13 are connected by solder bumps 5, respectively, and serve as one terminal for emitting light. The light emitting portion 2 of the light emitting element array chip 13 faces the fiber bundle 9.

【0026】上記構成のプリントヘツドにおいて、図5
の如く、発光素子アレイチツプ13の一端に半田バンプ
5を形成し、同時に、他端に傾斜防止用突起6を設け
る。
In the print head having the above structure, as shown in FIG.
As described above, the solder bump 5 is formed on one end of the light emitting element array chip 13, and at the same time, the tilt preventing projection 6 is provided on the other end.

【0027】次に、導体パターン10上にボンダーにて
転写法等によりフラツクス18を塗布し、その上に半田
バンプ5を接触させ、発光素子アレイチツプ13および
ICチツプ15を搭載する。発光素子アレイチツプ13
およびICチツプ15は、フラツクス18により仮接着
される。この際、突起6の接着点である絶縁被膜12に
はフラツクス18を塗布しないでおく。この状態で、図
6の如く、リフロー工程を通すことにより半田バンプ5
が熔融し、導体パターン10と接続される。同時に、突
起6が熔融し、絶縁被膜12に付着される。
Next, the flux 18 is applied to the conductor pattern 10 by a transfer method using a bonder, the solder bumps 5 are brought into contact with the flux 18, and the light emitting element array chip 13 and the IC chip 15 are mounted. Light emitting element array chip 13
The IC chip 15 and the IC chip 15 are temporarily adhered by the flux 18. At this time, the flux 18 is not applied to the insulating coating 12 which is the adhesion point of the protrusion 6. In this state, as shown in FIG. 6, the solder bumps 5
Melts and is connected to the conductor pattern 10. At the same time, the protrusions 6 melt and adhere to the insulating coating 12.

【0028】次に、アセトン、IPA等にてフラツクス
18を洗浄後、基板8と発光素子アレイチツプ13およ
びICチツプ15の間の空隙Xに、エポキシ樹脂等の材
料からなる透明樹脂20を、デイスペンサー等にて充填
する。この際、透明樹脂20は発光素子アレイチツプ1
3の傾斜防止用突起6側から注入する。
Next, after washing the flux 18 with acetone, IPA or the like, a transparent resin 20 made of a material such as an epoxy resin is placed in the space X between the substrate 8 and the light emitting element array chip 13 and the IC chip 15 with a dispenser. Etc. At this time, the transparent resin 20 is used as the light emitting element array chip 1.
It is injected from the inclination preventing projection 6 side of No. 3.

【0029】このとき、突起6側にフラツクスが塗布さ
れないため、フラツクスの残渣19がなく、透明樹脂2
0内にフラツクスが混入するのを防止できる。
At this time, since the flax is not applied to the side of the protrusion 6, there is no residue 19 of the flax and the transparent resin 2
It is possible to prevent the flux from being mixed into 0.

【0030】なお、半田バンプ5の周囲にはフラツクス
の残渣19が残つていることがあるが、透明樹脂20を
半田バンプ5と逆側から注入しているので、フラツクス
の残渣19が発光素子アレイチツプ13の光照射を遮る
位置に流れることはない。
A residue 19 of the flux may remain around the solder bump 5. However, since the transparent resin 20 is injected from the opposite side of the solder bump 5, the residue 19 of the flux is the light emitting element array chip. It does not flow to the position where the light irradiation of 13 is blocked.

【0031】その後、発光素子アレイチツプ裏面の共通
信号電極14に、例えば銀の粉末を混入したエポキシ樹
脂等の導電性樹脂21をデイスペンサー、マスク印刷等
にて塗布することにより共通電極パターン11に接続す
る。
Thereafter, the common signal electrode 14 on the back surface of the light emitting element array chip is connected to the common electrode pattern 11 by applying a conductive resin 21 such as an epoxy resin mixed with silver powder by a dispenser or mask printing. To do.

【0032】以上の動作により、300DPIの場合、
発光素子アレイチツプ13を直線上に40個配列し、発
光素子アレイチツプ13の発光部2は合計2560個直
線上に併置される。
By the above operation, in the case of 300 DPI,
Forty light emitting element array chips 13 are arranged on a straight line, and a total of 2560 light emitting portions 2 of the light emitting element array chips 13 are arranged on a straight line.

【0033】なお、本実施例はプリントヘツドの場合に
ついて説明したが本発明はそれに限るものではなく、発
光素子表示装置等、発光素子アレイチツプや受光チツプ
を搭載する全ての光学装置に使用できる。
Although the present embodiment has been described with respect to the case of the print head, the present invention is not limited to this, and it can be used for all optical devices such as a light emitting device display device having a light emitting device array chip or a light receiving chip.

【0034】[0034]

【発明の効果】本発明請求項1,2によると、発光素子
アレイチツプの一端に半田バンプを形成するとともに、
他端に傾斜防止用突起を設けているので、発光素子アレ
イチツプを面実装時に突起側にフラツクスを塗布せずに
おけば、その後、リフロー、洗浄する工程において、洗
浄液の流れが良くなつて洗浄性が向上し、従来のように
両サイドに半田バンプがあるために中央の発光部にフラ
ツクス残渣が残り光の透過の妨げになるのを防止でき
る。
According to claims 1 and 2 of the present invention, a solder bump is formed at one end of the light emitting element array chip, and
Since the protrusions for preventing tilt are provided on the other end, when the surface of the light-emitting element array chip is not coated with flux, the flow of the cleaning liquid is improved in the subsequent reflow and cleaning processes, and the cleaning performance is improved. It is possible to prevent the residue of the flux remaining in the central light emitting portion from interfering with the transmission of light due to the solder bumps on both sides as in the conventional case.

【0035】また、透明樹脂を、フラツクスが塗布され
ない傾斜防止用突起側から注入することで、従来のよう
に半田バンプ周囲に付着したフラツクス残渣が透明樹脂
に混入し光の透過の妨げになるのを防止できるといつた
優れた効果を有する。
Further, by injecting the transparent resin from the side of the inclination preventing protrusion where the flux is not applied, the residue of the flux adhered around the solder bumps is mixed into the transparent resin as in the conventional case, which hinders the transmission of light. It has an excellent effect when it can be prevented.

【図面の簡単な説明】[Brief description of drawings]

【図1】図1は本発明一実施例の光学装置の断面図であ
る。
FIG. 1 is a sectional view of an optical device according to an embodiment of the present invention.

【図2】図2は同じくその平面図である。FIG. 2 is a plan view of the same.

【図3】図3は同じく発光素子アレイチツプの正面図で
ある。
FIG. 3 is a front view of a light emitting element array chip of the same.

【図4】図4は同じくその断面図である。FIG. 4 is a sectional view of the same.

【図5】図5は同じく光学装置のリフロー前の状態を示
す断面図である。
FIG. 5 is a sectional view showing a state before reflow of the optical device, similarly.

【図6】図6は同じくそのリフローおよび洗浄後の状態
を示す断面図である。
FIG. 6 is a cross-sectional view showing a state after the reflow and the cleaning, similarly.

【図7】図7は従来の光学装置の断面図である。FIG. 7 is a sectional view of a conventional optical device.

【図8】図8は同じくその平面図である。FIG. 8 is a plan view of the same.

【図9】図9は同じく発光素子アレイチツプの正面図で
ある。
FIG. 9 is a front view of a light emitting element array chip of the same.

【図10】図10は同じくその断面図である。FIG. 10 is a sectional view of the same.

【図11】図11は同じく光学装置のリフロー前の状態
を示す断面図である。
FIG. 11 is a sectional view showing a state before reflow of the optical device, similarly.

【図12】図12は同じくそのリフローおよび洗浄後の
状態を示す断面図である。
FIG. 12 is a cross-sectional view showing a state after the reflow and the cleaning, similarly.

【符号の説明】[Explanation of symbols]

4 供給用電極 5 半田バンプ 6 傾斜防止用突起 8 基板 10 導体パターン 13 発光素子アレイチツプ 16 導体パターン 20 透明樹脂 X 空隙 4 Supply Electrode 5 Solder Bump 6 Tilt Prevention Protrusion 8 Substrate 10 Conductor Pattern 13 Light-Emitting Element Array Chip 16 Conductor Pattern 20 Transparent Resin X Void

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 発光素子アレイチツプからの照射光を基
板を通過させて外部へ照射するものであつて、前記発光
素子アレイチツプが透光性の基板上に空隙を有して面実
装され、空隙内の前記発光素子アレイチツプの電極と基
板上の導体パターンとの間に接続用の半田バンプが介在
され、前記空隙が透明樹脂にて封止された光学装置にお
いて、前記電極は、前記発光素子アレイチツプの一端部
にのみ配置され、該発光素子アレイチツプの他端部には
傾斜防止用の突起が設けられたことを特徴とする光学装
置。
1. A device for irradiating light emitted from a light-emitting element array chip to the outside through a substrate, wherein the light-emitting element array chip is surface-mounted with a void on a translucent substrate. In the optical device in which a solder bump for connection is interposed between the electrode of the light emitting element array chip and the conductor pattern on the substrate, and the gap is sealed with a transparent resin, the electrode is formed of the light emitting element array chip. An optical device characterized in that it is arranged only at one end, and a protrusion for preventing inclination is provided at the other end of the light emitting element array chip.
【請求項2】 発光素子アレイチツプの一端部に電極を
形成し、該電極に半田バンプを突出形成し、発光素子ア
レイチツプの他端に傾斜防止用の突起を突出形成し、前
記半田バンプにフラツクスを塗布し、該半田バンプを基
板上の導体パターンに接触させて仮接続し、発光素子ア
レイチツプと基板との間に基板を有したまま半田リフロ
ーして面実装し、空隙の突起側から透明樹脂を注入して
空隙を樹脂封止することを特徴とする光学装置の製造方
法。
2. An electrode is formed on one end of the light emitting element array chip, a solder bump is formed on the electrode, and a protrusion for preventing inclination is formed on the other end of the light emitting element array chip, and a flux is formed on the solder bump. Applying the solder bumps to the conductor pattern on the board for temporary connection, solder reflow with the board between the light emitting element array chip and the board for surface mounting, and transparent resin from the protruding side of the void. A method for manufacturing an optical device, which comprises injecting and sealing a void with a resin.
JP21868591A 1991-08-29 1991-08-29 Optical device and its manufacture Pending JPH0555633A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21868591A JPH0555633A (en) 1991-08-29 1991-08-29 Optical device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21868591A JPH0555633A (en) 1991-08-29 1991-08-29 Optical device and its manufacture

Publications (1)

Publication Number Publication Date
JPH0555633A true JPH0555633A (en) 1993-03-05

Family

ID=16723815

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21868591A Pending JPH0555633A (en) 1991-08-29 1991-08-29 Optical device and its manufacture

Country Status (1)

Country Link
JP (1) JPH0555633A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5891509A (en) * 1995-03-13 1999-04-06 Fujitsu Limited Method of applying a coating material to a plate with conveying rollers clamping side edges of the plate
WO2005052666A1 (en) * 2003-11-27 2005-06-09 Ibiden Co., Ltd. Ic chip mounting board, substrate for mother board, device for optical communication, method for manufacturing substrate for mounting ic chip thereon, and method for manufacturing substrate for mother board
US7070207B2 (en) 2003-04-22 2006-07-04 Ibiden Co., Ltd. Substrate for mounting IC chip, multilayerd printed circuit board, and device for optical communication
JP2009194201A (en) * 2008-02-15 2009-08-27 Oki Semiconductor Co Ltd Method of manufacturing semiconductor device and the semiconductor device
US8076782B2 (en) 2002-04-01 2011-12-13 Ibiden Co., Ltd. Substrate for mounting IC chip

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5891509A (en) * 1995-03-13 1999-04-06 Fujitsu Limited Method of applying a coating material to a plate with conveying rollers clamping side edges of the plate
US8076782B2 (en) 2002-04-01 2011-12-13 Ibiden Co., Ltd. Substrate for mounting IC chip
US8120040B2 (en) 2002-04-01 2012-02-21 Ibiden Co., Ltd. Substrate for mounting IC chip, manufacturing method of substrate for mounting IC chip, device for optical communication, and manufacturing method of device for optical communication
US7070207B2 (en) 2003-04-22 2006-07-04 Ibiden Co., Ltd. Substrate for mounting IC chip, multilayerd printed circuit board, and device for optical communication
US7693382B2 (en) 2003-04-22 2010-04-06 Ibiden Co., Ltd. Substrate for mounting IC chip, multilayered printed circuit board, and device for optical communication
WO2005052666A1 (en) * 2003-11-27 2005-06-09 Ibiden Co., Ltd. Ic chip mounting board, substrate for mother board, device for optical communication, method for manufacturing substrate for mounting ic chip thereon, and method for manufacturing substrate for mother board
JPWO2005052666A1 (en) * 2003-11-27 2008-03-06 イビデン株式会社 IC chip mounting substrate, motherboard substrate, optical communication device, IC chip mounting substrate manufacturing method, and motherboard substrate manufacturing method
US7437030B2 (en) 2003-11-27 2008-10-14 Ibiden Co., Ltd. Substrate for mounting IC chip, substrate for motherboard, device for optical communication, manufacturing method of substrate for mounting IC chip, and manufacturing method of substrate for motherboard
US7526152B2 (en) 2003-11-27 2009-04-28 Ibiden Co., Ltd. Substrate for mounting IC chip, substrate for motherboard, device for optical communication, manufacturing method of substrate for mounting IC chip, and manufacturing method of substrate for motherboard
JP2009194201A (en) * 2008-02-15 2009-08-27 Oki Semiconductor Co Ltd Method of manufacturing semiconductor device and the semiconductor device
US8435839B2 (en) 2008-02-15 2013-05-07 Lapis Semiconductor Co., Ltd. Method of manufacturing semiconductor device and the semiconductor device

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