JPS63113873A - Optical card reproducing device - Google Patents

Abstract

PURPOSE:To correctly read data even when a synchronizing signal cannot be detected due to the cause such as a drop-out by controlling the reading timing of the data of a card with a synchronizing signal detecting pulse or an interpolating pulse. CONSTITUTION:In the track of an optical card, a synchronizing signal and data are recorded. The output from a line sensor 14 to reproduce the optical card is binarized 21, and supplied to a PLL circuit 22 and a DFF23. The output of the FF23 is supplied to an AND circuit 24 and supplied to a shift register 25. The output of the register 25 is supplied to a digital comparator 26, a synchronizing signal detecting pulse PSY is supplied to a gate pulse generating circuit 27 and supplied to a NOR circuit 28. The output of the circuit 28 is supplied to a synchronizing counter 29 which is an interpolating means and supplied to the circuit 27. An interpolating pulse PH is synchronized to the pulse PSY, the circuit 27 cannot detect the pulse PSY, and even then, a correct gate pulse PG can be generated.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application The present invention relates to an optical card reproducing apparatus for reproducing an optical card on which synchronization signals and data are recorded.

B0 Summary of the Invention The present invention provides an optical card reproducing device for reproducing an optical card on which a synchronizing signal and data are recorded, for interpolating the synchronizing signal detection pulse based on the synchronizing signal detection pulse obtained by detecting the synchronizing signal. By forming an interpolation pulse of This is how it was done.

C0 conventional technology Traditionally, bank cards and credit cards.

Various optical cards (optical cards) having optical recording media as information recording media have been proposed for use in identification cards, other memory cards, and the like. For example, in an optical card in which a plurality of sub-tracks consisting of dot rows based on recording signals are formed in parallel along the longitudinal direction of the card, that is, in a stripe shape, each sub-trunk indicates the start of data, so A synchronization signal is added in front of the . In an optical card reproducing apparatus for reproducing such an optical card, when attempting to reproduce data on each sub-track, the synchronizing signal is usually detected first, and the subsequent portion is read out as data.

D0 Problems to be Solved by the Invention However, if a synchronization signal cannot be detected on a certain sub-track due to dropouts or other causes, the starting position of the data cannot be determined, and it is difficult to read out the data of that sub-track correctly. I couldn't.

The present invention was proposed in view of the above-mentioned conventional problems, and provides an optical card reproducing device that can read data correctly even if a synchronization signal cannot be detected due to dropouts or other causes. The purpose is to provide.

Means for Solving the E0 Problem In order to solve the above-mentioned problems, an optical card reproducing apparatus according to the present invention is an optical card reproducing apparatus for reproducing an optical card on which a synchronization signal and data are recorded. synchronous signal detection means for detecting a synchronous signal of a card and outputting a synchronous signal detection pulse; and interpolation means for outputting an interpolation pulse for interpolating the synchronous signal detection pulse based on the synchronous signal detection pulse; The present invention is characterized in that the read timing of card data is controlled by the synchronization signal detection pulse or the interpolation pulse.

F0 effect According to the present invention, when a synchronization signal cannot be detected,
Data read timing is controlled by interpolation pulses.

G. Example Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

First, the optical card in this embodiment will be explained with reference to FIG. A rectangular optical card 1 having an optical recording medium on a substrate has a plurality of sub-trunks T consisting of dot rows based on recording signals arranged in parallel along the longitudinal direction of the card (direction of arrow A), that is, in a stripe shape. It is made up of. The signals recorded as the sub-tracks T are composed of a synchronizing signal S and subsequent data D (information signal). The above synchronization signal SV is
For example, it is a predetermined pattern consisting of 8 bits.

Furthermore, since each sub-track T is arranged orderly in the longitudinal direction of the card, the above-mentioned synchronization signal S on the optical card l
The positions (heights) of Y and data D are each constant, and are lined up in a line in the longitudinal direction of the card.

Next, a reproducing apparatus for reproducing the optical card 1 as described above will be explained. Figure 3 shows the configuration of the optical system.
Figure 1 shows the configuration of the signal processing system.

In the third leap, illumination light from an LED (light emitting diode) 11 is focused by a condenser lens 12 and irradiated onto an area on the optical card 1 including one sub-trunk. The reflected light is focused by an objective lens 13, formed into an image on the light receiving surface of a line sensor 14 made of a CCD (charge coupled device), and converted into an electrical signal. As the line sensor 14, for example, one with 1024 channel bits is used, and the optical magnification is set so that 4 channel bits are distributed to 1 data bit. Further, the line sensor 14 scans in the direction of arrow B perpendicular to the longitudinal direction of the card (direction of arrow A).
Assuming one data blocker for each bit, 1024
1 channel clock or 256 data clocks
Scanning is performed periodically.

Further, the optical card 1 is transported at a constant speed in the longitudinal direction of the card by capstans 15a, 15b and pinch rollers 16a, 16b. The transfer speed is such that the line sensor 14 scans four times per one tora.7. Data of each sub-trunk T is read out with one scan out of these four scans being valid.

Next, in FIG. 1 showing the configuration of the signal processing system, the output from the line sensor 14 is binarized by the binarization circuit 21, and then converted into PLL (Phase Locked Loo
p) are supplied to the data input terminals (D) of the circuit 22 and the D flip-flop 23, respectively. The data clock φ from the PLL circuit 22 is connected to the D flip-flop 23.
They are also supplied to a shift register 25° synchronization counter 29, which will be described later. The output from the output terminal (Q) of the D flip-flop 23 is supplied to an AND circuit 24 and also to a serial/parallel output shift register 25.

The output from the D flip-flop 23, which has been subjected to serial/parallel conversion by the shift register 25, is supplied to a digital comparator 26, which is a synchronization signal detection means.
For example, it is compared with a predetermined 8-bit synchronization signal pattern. The output from the digital comparator 26, that is, the synchronization signal detection pulse psv, is transmitted to the gate pulse generation circuit 27.
It is also supplied to one input terminal of the NOR circuit 28. The output from the output terminal of the NOR circuit 28 is the negative clear terminal (τ
τ below). Further, the interpolation pulse P8 outputted from the output terminal of the synchronization counter 29 is supplied to the gate pulse generation circuit 27, and is also supplied to the NOR circuit 2.
8 is supplied to the other input terminal. The above synchronization counter 29
is the data clock φ supplied from the PLL circuit 22. This is a 256-loop counter that counts , and an interpolation pulse P8 synchronized with the synchronization signal detection pulses P and 7 is output every 256 counts. The gate pulse generation circuit 27 generates a gate pulse PG having a pulse width corresponding to the data D portion of the sub-track T in response to the synchronization signal detection pulses p, v or the interpolation pulse P.
This gate pulse P generates the above-mentioned A
By being supplied to the ND circuit 24, the AND circuit 2
Data D of each sub-trunk T is output from 4. That is, gate pulse P. The read timing of the data D is controlled by the synchronization signal detection pulse psv or the interpolation pulse P which is the source of generating the data D. Specifically, the synchronization signal detection pulse p
sv or the next data bit of the interpolation pulse PM, the gate is opened and data D is read out.

Next, the operation will be explained in more detail while also referring to the time chart shown in FIG.

Now, consider a case where the line sensor 14 outputs a signal as shown in FIG. 4(A). That is, consider a case where the synchronization signal Sv was successfully read for the m-th sub-track, but the synchronization signal was not successfully read for the m+1-th sub-track due to a dropout or the like. First, focusing on the m-th sub-track, the digital comparator 26 detects the synchronization signal S7, and outputs the synchronization signal detection pulse psv as shown in FIG. 4(B). By supplying this synchronizing signal detection pulse psv, the gate pulse generation circuit 27 outputs a gate pulse Pc as shown in FIG. 4(C). As a result, as shown in FIG. 4(E), data D is output from the AND circuit 24. Further, the value of the synchronization counter 29 is cleared by the synchronization signal detection pulse psv. As a result, the synchronization counter 29 outputs an interpolation pulse P8 as shown in FIG. 4(D). This interpolation pulse P is synchronized with the synchronization signal detection pulse psv, and continues to be output every time the line sensor 14 is synchronized with the scan.

Next, looking at the m+1th sub-track, since the synchronization signal was not read properly, the digital comparator 26 does not detect the synchronization signal, and therefore no synchronization signal detection pulse is output. However, the interpolation pulse P from the synchronization counter 29. Since this interpolation pulse P4 causes the gate pulse generation circuit 27 to output a gate pulse P0 as shown in FIG. 4(C). Therefore, as shown in the 41st EI (E),
Data D from the AND circuit 24. 1 is output.

In this way, even if the synchronization signal of a certain sub-track cannot be detected, the data start position can be determined by the interpolation pulse P, that is, the gate pulse P can be generated, and the data can be read out correctly. be able to.

Note that as the optical card 1 moves in the longitudinal direction, the channel position of the line sensor 14 may shift with respect to the sub-track T;
Since the channel bits are distributed, even if the channel bits are moved to an adjacent trunk, the shift in channel position is negligible.

Therefore, it is safe to assume that the synchronization signal patterns of the adjacent trunks appear at the same position (timing) of the scanning period jlJll of the licensor 14. Therefore, the synchronization signal SV
If the data D cannot be detected, it can be said that controlling the read timing of the data D using the interpolation pulse P is an extremely effective method.

H0 Effects of the Invention As is clear from the description of the embodiments described above, according to the optical card reproducing apparatus of the present invention, an interpolation pulse for interpolating the synchronization signal detection pulse is formed based on the synchronization signal detection pulse. Therefore, even if the synchronization signal cannot be detected due to dropout or the like, the data readout timing can be controlled by the interpolation pulse, and the data can be read out correctly.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a signal processing system in an embodiment of the optical card reproducing device according to the present invention, FIG. 2 is a diagram schematically showing the same optical card, and FIG. 3 is the same configuration of the optical system. FIG. 4 is a time chart for more specifically explaining the operation of the signal processing system. l...Optical card 26...Digital comparator 29...Synchronization counter

Claims (1)

[Scope of Claim] An optical card reproducing device for reproducing an optical card on which a synchronization signal and data are recorded, comprising: synchronization signal detection means for detecting a synchronization signal of the optical card and outputting a synchronization signal detection pulse; and an interpolation means for outputting an interpolation pulse for interpolating the synchronization signal detection pulse based on the detection pulse, and the light source is configured to control the reading timing of the data of the card by the synchronization signal detection pulse or the interpolation pulse. Card playback device.