JPS6310908B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device with improved characteristics.

Due to the presence of a large internal negative feedback resistance, a conventional field effect transistor has a drain voltage-current characteristic exhibiting a saturation characteristic of a pentode vacuum tube type. However,
The electrostatic induction field effect transistor SIT proposed and realized by the inventor of the present application has an extremely small internal negative feedback resistance r _s , so that r _s ·G _n <<1, and exhibits a triode vacuum tube type rise characteristic.

The present invention has the advantage that the internal negative feedback resistance of an electrostatic induction field effect transistor is extremely small compared to the internal resistance of a conventional field effect transistor exhibiting pentode type saturation characteristics, and that the negative feedback resistance can be easily controlled from the outside. It's rooted. In other words, an impedance Z _s having a frequency characteristic is inserted in series with the source of the electrostatic induction field effect transistor, and the relationship Z _s・G _n ≪1 is satisfied only for the desired signal frequency, thereby reducing the amount of negative feedback. For signals in other frequency ranges, Z _s ·G _n ≫1, and a large negative feedback effect is exerted.

The present invention will be explained in detail below.

The principle of the present invention will be explained using FIG. G,
S and D are the gate, source, and drain of the electrostatic induction field effect transistor 1, respectively, V _io is the input signal, V _DD is the drain bias voltage, R _l is the load resistance, and Z _s is connected in series with the source. represents the impedance. The apparent mutual conductance G′ _n when there is a negative feedback effect is expressed as G′ _n = G _n /1 + Z _s・G _n , and the amount of negative feedback is small only when Z _s・G _n ≪1. , G′ _n =G _n , indicating a triode-type rise characteristic. Conversely, when Z _s ·G _n ≫1, the amplification degree decreases due to a large negative feedback effect. When Z _s・G _n ≪1, the amplification degree K of this circuit can be calculated by simple calculation as long as the capacitance can be ignored: K=-μR _l /R _l +r _d + (1+μ)Z _s ……(1) becomes. Here, r _d is the internal resistance, μ is the amplification factor specific to the electrostatic induction field effect transistor, and W is the angular frequency used. In the high frequency region, the amplification degree K becomes small due to the presence of capacitance. Various types of Z _s can be considered, but any type may be used as long as it has nonlinearity with respect to frequency.
As shown in the figure. Now, the simplest capacitance C _s in Figure 2 a
An example will be explained in which a parallel circuit of R and R _s is connected in series to the source. In equation (1), Z _s = (jωc
+1/R _s ) ^-1 impedance is substituted, we get
The amplification degree K is as follows.

K=-μR _l /R _l +r _d +(1+μ)R _s・1+jωc _s R _s /1
+jωc _s R _s (r _d +R _l )/R _l +r _d + (1+μ)R _s ……(2) In the low frequency region, equation (2) is K ₀ =−μR _l /R _l +r _d + (1+μ) R _s ...(3) In the high frequency region, K ₁ = -μR _l /r _d + R _l ...(4). From the above equations (3) and (4), it can be seen that the parallel impedance of C _s and R _s has a large negative feedback effect in the low frequency region and reduces the amplification degree K. Conversely, in the high frequency range, the negative feedback effect is reduced,
The degree of amplification does not decrease. This situation is shown in FIG. 3a.

Since the internal resistance r _d of the electrostatic induction field effect transistor is at least four orders of magnitude smaller than that of a conventional field effect transistor having saturation characteristics, the amplification factor can be made approximately equal to μ in the high frequency region.
If the circuit shown in FIG. 2a is used, the degree of amplification in the low frequency region is small, so it is possible to efficiently suppress low frequency noise. This circuit also has an automatic bias function. That is, a bias voltage of V _g =-I _d ·R _s is automatically applied to the gate of the field effect transistor 1 by the drain current I _d . The bias point is stably maintained by the negative feedback effect of R _s . On the other hand, high frequency signals flow through the bypass capacitor _Cs and are not subject to large negative feedback effects. Therefore, the amplification degree in the high frequency region does not change at all by inserting the parallel circuit of C _s and R _s .

It seems clear from the above example that the operating characteristics of the electrostatic induction field effect transistor 2 change largely depending on the frequency due to the negative feedback impedance that changes non-linearly with respect to the frequency applied in series to the source. .

The circuit examples other than those shown in FIG. 2a are similar in that Z _s changes nonlinearly with respect to frequency. Figure 2 a acts as a kind of high-pass filter, and b acts as a low-pass filter.The impedance becomes smaller in the high and low frequency regions, respectively, and the amount of negative feedback decreases, so the amplification degree K changes accordingly. It increases as shown in Figure 3a and b.

FIGS. 2c and 2d use parallel and series resonant circuits as Z _s , respectively, and the impedance reaches its maximum and minimum at the resonant frequency ω ² =1/LC, respectively. Therefore, as shown in FIG. 4, the amplification degree K is minimum at the parallel resonance frequency and maximum at the series resonance frequency. All of the circuit examples shown in Figure 2 have a filter effect, and the common feature is that the amplification degree of the static induction transistor 1 is controlled by changing the negative feedback impedance in a certain fixed frequency range. are doing.
These circuits are just examples, and it goes without saying that any circuit, passive or active, is effective as long as its impedance is frequency dependent.

For example, a twin-tay circuit or various filter groups used for frequency selection of a selective amplifier, typically an active filter whose main component is a ceramic filter active element, etc., can be mentioned.

These circuits are constructed using individual components, and
It goes without saying that monolithic integration on a solid state or use of a hybrid integrated circuit will work effectively. A case in which the parallel circuit of capacitance and resistance shown in FIG. 2a is integrated in S _i will be specifically explained below.

In Figure 5, a layer of conductivity type opposite to the channel is provided on the source side, a junction capacitance is used as a bypass capacitor, and a resistor R _s is created by a window penetrating a part of the layer of opposite conductivity type and connected to the channel with the same conductivity type. This is an example where . Figure a is an example in which the present invention is applied to a buried gate type n-channel static induction transistor, in which most of the source side semiconductor surface is a p-type region 2.
4, and a window 17 for the n-type region is partially opened. The resistance R _s and the capacitor C _s can be controlled by their respective surface areas, but the n-type layer 16 and the p-type layer 24
Alternatively, by providing at least a part of the n-type region 19 between the n-type layer 17, the resistance R _s and the capacitance C _s
control is possible. Figures b and c show examples in which the structure of the present invention is applied to an inverted electrostatic induction transistor. In figure b, the source high impurity concentration (n ⁺ ) region 18 near the opening 17 of the opposite conductivity type region 24 is replaced with an i or n ^- region having a lower impurity concentration. By adjusting the impurity concentration in this region, the resistance value can be adjusted. FIG. 5c shows an example in which the center of the opening and the center of the channel are shifted to intentionally lengthen the current path length, and the resistance is increased accordingly. In this way, by adjusting the opening of the opposite conductivity type region formed in contact with the source region, the capacitance can be increased, and by adjusting the impurity concentration of the source region near the opening, the resistance can be increased. Adjustable, negative feedback impedance can be efficiently inserted into the source circuit.

Other embodiments of the present invention are listed below for reference.

FIG. 6a is a cross section of an n-channel vertical field effect transistor having a p-type buried gate 13, including a drain electrode 11, an n-type high impurity density region 14, an n-type low impurity density region 15, and a channel consisting of the gate 13. through the n-type low impurity density region 1
5 in a row.

On the source side, a window is opened in a thin film 18 of an insulating material such as SiO ₂ , Si ₃ N ₄ , Al ₂ O _{3 ,} etc., and the source electrode 12 is in contact with the insulating film 18 and the n-type high impurity density region 17 . The smaller the size of this window is, the larger the resistance R _{s becomes} . growing. If necessary, the value of the resistance R _s can be controlled by providing a high resistance region 19 such as a low impurity density or intrinsic region adjacent to the source side n-type high impurity density region 17 as shown by the dotted line in the figure. can do. Furthermore, the n-type region 17 may be in contact with the entire surface of the insulating film 18. FIG. 6b shows an example in which the present invention is applied to a vertical field effect transistor provided with a step structure, and is based on the same idea as in a. In the figure, the source high impurity density region 17 has a convex portion because
This is based on the "Field Effect Transistor" proposed by the present inventor in Japanese Patent Publication No. 56-26148, which does not increase the capacitance between the gate region 13 and reduces the channel resistance r _s .
The value of the resistance R _s can be maximized if the window 8 is placed directly under the gate 3 as shown in the figure, but the position is arbitrary and is determined by the design. 6c and d show an example in which a similar idea of the invention is applied to a lateral field effect transistor. It consists of parts that touch each other. Although the n-type region 17' is not necessarily required, the n-type regions 17 and 17' may be integrated, but by providing the P-type region 21 between them as shown in Figure c, the resistance R _s can be reduced. Can be made larger. Furthermore, the P type region 21 is the n region 1
7 and 17', and may be provided here and there in the n-type low impurity density region 15 between 17 and 17', depending on the size, depth, spacing, etc., and the size of the window. The resistance R _s can be controlled by d is
It is an insulated gate type field effect transistor, and the gate 13 is connected to the source region 17 and the source region 17 through the insulating film 18.
17' and the drain region 14 is a P-type substrate 20.
Forms a channel near the surface. In this case, even if the source regions 17 and 17' are integrated, as shown in the figure, the n-type layer 2
It may also be connected via 2. With the n-type layer 22, the resistance R _s can be effectively controlled.

The above is a case in which the source electrode metal consists of a portion that is in direct contact with the semiconductor and a portion that is in contact with the semiconductor through an insulating film, but it is also effective to use a metal that has a high contact resistance with the semiconductor.

The present invention can also be realized by providing a semi-insulating material layer such as TiO ₂ between the source semiconductor region and the source electrode metal or between the source electrode metal. In the case of a buried gate, a layer of semi-insulating material can be provided over the entire surface or in part; another example is shown in FIG. a
1 is an example in which the present invention is applied to a vertical field effect transistor having a notch structure having a gate 13 on the side wall of a recess, and the source side is composed of an electrode 12, a semi-insulating material layer 23, and a high impurity density layer 17. Semiconductor region 17 is not necessarily required. Figures b and c are examples in which the present invention is applied to surface-wiring type vertical field effect transistors, and in particular, figure c has a semi-insulating material layer between the source electrode metals.

The inductance L in FIGS. 2b, c, and d can be integrated on the same Si substrate using well-known reactance diodes and reactance transistors.

Next, a specific example using a hybrid integrated circuit is shown in FIG.

The inductance L is made by vapor deposition etc.
Combines with monolithic IC part. 30 is a source electrode, 31 is an inductance patterned by vapor deposition or the like, 32 is a coupling electrode, 33 is a semi-insulating film, 34 is a source diffusion region, 35 is SiO ₂ ,
A and B indicate cross-sectional locations. In this way, an inductance L is connected between the source electrode 30 and the source diffusion region 34 in parallel to the resistance R and capacitance C of the semi-insulating film.
can be added, and the circuit shown in FIG. 2c can be realized.

As detailed above, the present invention controls the amount of negative feedback as a function of frequency by connecting an external additional circuit having frequency characteristics in series to the source of a small electrostatic induction field effect transistor when the internal negative feedback resistor is small. By appropriately selecting the circuit, circuits with various operating characteristics can be easily realized using individual components as well as hybrid and monolithic integrated circuits.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram for explaining the principle of the present invention, Fig. 2 is a circuit example of a circuit corresponding to Z _s in Fig. 1, and Figs. 3 and 4 are respectively shown in Fig. 2 a to d. Characteristic examples showing the corresponding characteristics, FIGS. 5 to 7 are one embodiment of the present invention, and are cross-sectional views when integrated on a solid body, and FIG. 8 is a cross-sectional view of another embodiment of the present invention. This is an example of a hybrid integrated circuit.

Claims (1)

[Claims] 1. A source high impurity concentration region of one conductivity type and its electrode formed in contact with one main surface of a semiconductor substrate, and a high impurity concentration region of one conductivity type drain formed in contact with the other main surface. In a static induction transistor comprising a doped region and its electrode, and a highly doped gate region of one conductivity type and an opposite conductivity type that is embedded in the semiconductor substrate and defines a plurality of channels and its electrode, the source region is , through an opening in a semiconductor region of the opposite conductivity type that is provided in contact with one main surface and mainly forms a capacitance, to a semiconductor region of the same conductivity type that mainly forms a resistance and has a lower impurity concentration than the source region. A semiconductor integrated circuit device comprising at least one static induction transistor having a connecting structure. 2. The semiconductor integrated circuit device according to claim 1, comprising at least one static induction transistor in which the center of the opening of the opposite conductivity type semiconductor region and the center of the channel do not coincide with each other. 3. A source high impurity concentration region of one conductivity type and its electrode formed in contact with one main surface of the semiconductor substrate, and a drain high impurity concentration region of one conductivity type formed in contact with a part of the other main surface and its electrode. ,
In a static induction transistor formed in contact with a part of the other main surface and comprising a gate region of high impurity concentration of one conductivity type and an opposite conductivity type defining a channel region and its electrode, the transistor is formed in contact with the source region. 1. A semiconductor integrated circuit device comprising at least one static induction transistor of one conductivity type and the opposite conductivity type, which has a structure connected to a channel region through an opening in a semiconductor region mainly forming capacitance. 4. The semiconductor integrated circuit device according to claim 3, comprising at least one static induction transistor in which the center of the opening of the opposite conductivity type region and the center of the channel do not coincide with each other.