JPS63108872A - Horizontal deflecting circuit - Google Patents

Horizontal deflecting circuit

Info

Publication number
JPS63108872A
JPS63108872A JP25418786A JP25418786A JPS63108872A JP S63108872 A JPS63108872 A JP S63108872A JP 25418786 A JP25418786 A JP 25418786A JP 25418786 A JP25418786 A JP 25418786A JP S63108872 A JPS63108872 A JP S63108872A
Authority
JP
Japan
Prior art keywords
pulse
voltage
circuit
current
horizontal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP25418786A
Other languages
Japanese (ja)
Inventor
Hideo Tomita
英夫 富田
Shinji Wakita
真治 脇田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP25418786A priority Critical patent/JPS63108872A/en
Publication of JPS63108872A publication Critical patent/JPS63108872A/en
Pending legal-status Critical Current

Links

Landscapes

  • Details Of Television Scanning (AREA)

Abstract

PURPOSE:To remove the discontinuous part and to have the same inclination in a horizontal deflecting current during an effective scanning period by passing all current passing through a damper diode to a bidirectional switching element. CONSTITUTION:In place of a horizontal deflecting output transistor and the damper diode, a MOSFET 6 as the bidirectional switching element is used. The terminal voltage VC of a capacitor C1 is compared with a reference voltage VS, when the voltage VC exceeds the VS, a signal SC is outputted from a comparator 7. According to the rise of this signal SC, a monostable multivibrator 8 having a time constant tauS is triggered to obtain a pulse P1 of a pulse duration tauS. This pulse P1 and a horizontal driving pulse HD are applied to an OR circuit 9 and this output pulse P2 is applied to the gate electrode of an FET6. Thereby, the difference in the effective scanning period is eliminated to obtain the horizontal deflecting current having to constant inclination.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はテレビ受像機の水平偏向回路に関するものであ
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a horizontal deflection circuit for a television receiver.

〔発明の概要〕[Summary of the invention]

本発明は、双方向性スイッチと共振コンデンサと水平偏
向コイルとを並列に接続すると共に、それらの共通接続
点の電圧と基準電圧とを比較して上記共通接続点の電圧
が上記基準電圧を越えたことを検出し、その検出信号に
基いて所定巾のパルスを発生させ、このパルスと水平駆
動パルスとを論理和回路に供給し、その論理和出力によ
り上記双方向性スイッチ素子を制御するようにしたこと
により、従来の水平出力トランジスタの逆方向電流に基
く、水平偏向電流の不連続性を除去するようにしたもの
である。
The present invention connects a bidirectional switch, a resonant capacitor, and a horizontal deflection coil in parallel, and compares the voltage at their common connection point with a reference voltage so that the voltage at the common connection point exceeds the reference voltage. A pulse of a predetermined width is generated based on the detection signal, and this pulse and a horizontal drive pulse are supplied to an OR circuit, and the output of the OR circuit controls the bidirectional switching element. By doing so, discontinuity in the horizontal deflection current due to the reverse current of the conventional horizontal output transistor is removed.

〔従来の技術〕[Conventional technology]

第3図は従来のテレビ受像機−におけろ水平偏向回路を
示す。
FIG. 3 shows a horizontal deflection circuit in a conventional television receiver.

第3図において、十B電源が供給される端子1にフライ
バックトランスの1次側コイル2の一端が接続され、こ
の1次側コイル2の他端と接地間には、水平出力トラン
ジスタ3、ダンパダイオードD、共振コンデンサCI及
び水平偏向コイル4とS字補正コンデンサcmとの直列
回路が並列に接続されている。上記トランジスタ3のベ
ースには端子5より水平駆動パルスHDが供給されて、
このトランジスタ3をスイッチング制御している。
In FIG. 3, one end of a primary coil 2 of a flyback transformer is connected to a terminal 1 to which a 10B power supply is supplied, and a horizontal output transistor 3, A series circuit including a damper diode D, a resonant capacitor CI, a horizontal deflection coil 4, and an S-shaped correction capacitor cm are connected in parallel. A horizontal drive pulse HD is supplied to the base of the transistor 3 from the terminal 5,
Switching of this transistor 3 is controlled.

上記パルスHDは第4図に示すように水平走査期間Hに
おける帰線期間と有効走査期間の一部とを含む期間T、
で「L」 (低レベル)となり・有効走査期間の大部分
の期間T!でrHJとなっている。
As shown in FIG. 4, the pulse HD includes a period T including a blanking period in the horizontal scanning period H and a part of the effective scanning period;
It becomes “L” (low level) at T!, which is the majority of the effective scanning period. It is rHJ.

第3図及び第4図において、パルスHDが「H」のとき
トランジスタ3がONとなり、+B[源からコイル2を
通じて電流I、が流れると共にコイル4に水平偏向電流
Ieyが流れて、有効走査が行われる。パルスHDがr
LJになるとトランジスタ3がOFFとなり、+Bt源
からの電流はコンデンサC1を充電する。これによって
コンデンサCIの端子にパルス状の電圧vcが発生し、
このvcの発生期間に逆方向の電流layが流れて帰線
走査が行われる。この帰線走査の終了後、コンデンサC
2よりダイオードDに電流toが流れ、その途中でパル
スHDが再びrHJになってトランジスタ3がONとな
り、再び電流1B、lnyが流れて有効走査が行われる
In FIGS. 3 and 4, when pulse HD is "H", transistor 3 is turned on, current I flows from the +B source through coil 2, and horizontal deflection current Iey flows through coil 4, resulting in effective scanning. It will be done. Pulse HD is r
When LJ is reached, transistor 3 is turned off, and the current from the +Bt source charges capacitor C1. This generates a pulse-like voltage vc at the terminal of the capacitor CI,
During the generation period of this vc, a current lay flows in the opposite direction and retrace scanning is performed. After completing this retrace scan, capacitor C
Current to flows from 2 to diode D, and in the middle of this, pulse HD becomes rHJ again, transistor 3 is turned on, currents 1B and lny flow again, and effective scanning is performed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

第3図の上述した動作において、上記電流■。 In the above-described operation of FIG. 3, the above-mentioned current ■.

は理論的にはその全部がダイオードDを流れ、略ゼロに
なったときトランジスタ3がONとなって有効走査期間
の電流layに引き継がれることになっている。しかし
ながら実際には、上記16が流れている途中でトランジ
スタ3がONになると、第4図の「転流」の文字で示す
ように、このI。
Theoretically, all of the current flows through the diode D, and when it becomes approximately zero, the transistor 3 is turned on and is passed on to the current lay during the effective scanning period. However, in reality, if the transistor 3 is turned on while the above-mentioned signal 16 is flowing, this I will be turned on as indicated by the letter "commutation" in FIG.

の一部がトランジスタ3のエミッタからコレクタ側への
逆方向電流となって転流することが確認されている。− その場合、ダイオードDのスレッシッルド電圧v7エ(
′=NO37v)とトランジスタ3のコレクタ・エミッ
タ間飽和電圧Vctsat  (’qo、2 V)との
違いによって、第4図のように電圧vcに段差が生じる
と共に、この段差の部分で電流1.の傾斜が異る不連続
部分が生じる。この不連続部分によって、テレビ画面に
おいては、画面の左側では走査が速くなり、右側では走
査が遅くなる。このため、画面の左側は暗くなると共に
画像が横方向に伸び、画面の右側は明るくなると共に画
像が横方向に縮むと云う問題が生じる。
It has been confirmed that a part of the current is commutated as a reverse current from the emitter to the collector of the transistor 3. - In that case, the threshold voltage v7 of diode D (
Due to the difference between the collector-emitter saturation voltage Vctsat ('qo, 2 V) of the transistor 3 and the collector-emitter saturation voltage Vctsat ('qo, 2 V) of the transistor 3, a step occurs in the voltage vc as shown in FIG. A discontinuous portion with a different slope occurs. This discontinuity causes a television screen to scan faster on the left side of the screen and slower on the right side. This causes a problem in that the left side of the screen becomes darker and the image stretches horizontally, while the right side of the screen becomes brighter and the image shrinks laterally.

この問題はインデックス方式カラー陰極線管等のように
超精密な水平リニアリティを要求される受像管を用いた
受像機において特に顕著であり、改善を求められていた
ものである。
This problem is particularly noticeable in picture receivers that use picture tubes that require ultra-precise horizontal linearity, such as index-type color cathode ray tubes, and has been in need of improvement.

〔問題点を解決するための手段〕[Means for solving problems]

本発明においては、上記ダンパダイオードDを省略する
と共に、上記トランジスタに代えてパワーMO3−FE
T等の双方向性スイッチング素子を用いている。これと
共に上記双方向性スイッチと上記共振コンデンサと上記
水平偏向コイルとの上記電源側における共通接続点の電
圧と基準電圧とを比較し、上記共通接続点の電圧が上記
基準電圧を越えたことを検出する比較回路と、上記比較
回路から得られる検出信号に基いて所定巾のパルスを発
生する回路と、上記パルスと水平駆動パルスとが供給さ
れて、その出力信号により上記双方向性スイッチ素子を
制御する論理°和回路とを設けている。
In the present invention, the damper diode D is omitted and a power MO3-FE is used instead of the transistor.
A bidirectional switching element such as T is used. At the same time, the voltage at the common connection point on the power supply side of the bidirectional switch, the resonant capacitor, and the horizontal deflection coil is compared with a reference voltage, and it is determined that the voltage at the common connection point exceeds the reference voltage. A comparison circuit for detecting, a circuit for generating a pulse of a predetermined width based on the detection signal obtained from the comparison circuit, and the pulse and the horizontal driving pulse are supplied, and the output signal drives the bidirectional switching element. A logical sum circuit for control is provided.

〔作用〕[Effect]

従来のダンパダイオードに流れていた電流の全てを双方
向性スイッチング素子に流すことができるので、前述し
た水平偏向電流の不連続部分が除去され、有効走査期間
において水平偏向電流を同じ傾斜で流すことができる。
Since all of the current flowing through the conventional damper diode can be passed through the bidirectional switching element, the discontinuous portion of the horizontal deflection current mentioned above is removed, and the horizontal deflection current can be made to flow at the same slope during the effective scanning period. Can be done.

〔実施例〕〔Example〕

第1図は本発明の実施例を示し、第3図と同一部分には
同一符号を付してその説明を省略する。
FIG. 1 shows an embodiment of the present invention, and the same parts as those in FIG. 3 are given the same reference numerals, and the explanation thereof will be omitted.

本実施例においては、第3図におけるダンパダイオード
Dを省略すると共に、トランジスタ3に代えて双方向性
スイッチング素子としてのパワーMO3−FET(以下
単にFETと称する)6を用いている。これと共にコン
デンサC3の端子電圧VCと基準電圧V、とをコンパレ
ータ7で比較し、VCがV、を越えたときに、このコン
パレータ7より、第2図に示すようなrHJに立上る信
号Scを得るようにしている。上記V、は前記ダンパダ
イオードDのスレッシッルド電圧vT、と対応する大き
さに選ばれている。
In this embodiment, the damper diode D in FIG. 3 is omitted, and the transistor 3 is replaced by a power MO3-FET (hereinafter simply referred to as FET) 6 as a bidirectional switching element. At the same time, the terminal voltage VC of the capacitor C3 and the reference voltage V are compared by the comparator 7, and when VC exceeds V, the comparator 7 outputs a signal Sc that rises to rHJ as shown in FIG. I'm trying to get it. The above V is selected to have a magnitude corresponding to the threshold voltage vT of the damper diode D.

上記信号Scの立上りによって時定数τ3を有するモノ
マルチ8をトリガし、このモノマルチ8より第2図に示
すようなパルス巾τ3のパルスP。
The rise of the signal Sc triggers the monomulti 8 having a time constant τ3, and the monomulti 8 generates a pulse P with a pulse width τ3 as shown in FIG.

を得る。このパルスP、は図示のようにパルスHDのT
8期間(「H」の期間)の一部と重複して得られるよう
に、上記時定数τ$が選ばれている。
get. This pulse P is T of pulse HD as shown in the figure.
The above time constant τ$ is selected so that it overlaps with a part of the 8 periods (“H” period).

このパルスP1とパルスHDとをオアゲート9に加え、
このオアゲート9より第2図に示すようなパルスP、を
得、このパルスP8をFET6のゲート電極に加えるよ
うにしている。
Adding this pulse P1 and pulse HD to the OR gate 9,
A pulse P as shown in FIG. 2 is obtained from this OR gate 9, and this pulse P8 is applied to the gate electrode of the FET 6.

以上によれば、上記パルスP8はパルス状の電圧vcが
発生する帰線期間のみrLJとなり、従ってこの帰線期
間のみFET6がOFFとなる動作が行われる。この結
果、有効走査期間の前半において従来のダンパダイオー
ドに流れていた電流I・はその全部がFET6のON期
間の前半で流れ、後半では上記電流!、と同一傾斜で電
流!。。
According to the above, the pulse P8 becomes rLJ only during the retrace period in which the pulse-like voltage vc is generated, so that the FET 6 is turned off only during this retrace period. As a result, all of the current I. flowing through the conventional damper diode in the first half of the effective scanning period flows in the first half of the ON period of FET 6, and in the second half, the above current ! , and the current with the same slope! . .

が流れるので、前述した第4図の電流1.における不連
続部分をなくすことができる。
flows, so the current 1. in FIG. 4 mentioned above flows. The discontinuous part in can be eliminated.

〔発明の効果〕〔Effect of the invention〕

従来の水平出力トランジスタの逆方向電流により生じる
水平偏向電流の不連続部分を除去することができる。従
って、本発明は特にインデックス方式カラー陰極線管等
のように超精密なリニアリティ補正を要求される受像管
を用いたテレビ受像機に用いて有効である。
Discontinuities in horizontal deflection current caused by reverse current in conventional horizontal output transistors can be eliminated. Therefore, the present invention is particularly effective for use in television receivers using picture tubes that require ultra-precise linearity correction, such as index type color cathode ray tubes.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例を示す回路図、第2図は第1図
の動作を説明するためのタイミングチャート、第3図は
従来の水平偏向回路の回路図、第4図は第3図の動作を
説明するためのタイミングチャートである。 なお図面に用いた符号において、 1・−・−−−−−−−−−−一−・・・−・電源端子
4・−・・・−・−・−・・・−・・水平偏向コイル6
・−・−・−・−・−−−一−−−・パワーMO3−F
ETC3−・・−・・−・・−・共振コンデンサC! 
−−−−−−−・−−−一−・−8字補正コンデンサ7
・−・−・−−−−m−−−−−−・・コンパレータ8
−・・・・−・・−・−・・・−・・モノマルチ9・−
・・・−・・−・・・・−・−・・オアゲートである。
Fig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a timing chart for explaining the operation of Fig. 1, Fig. 3 is a circuit diagram of a conventional horizontal deflection circuit, and Fig. 4 is a circuit diagram of a conventional horizontal deflection circuit. 5 is a timing chart for explaining the operation shown in the figure. In addition, in the symbols used in the drawings, 1. coil 6
・−・−・−・−・−−−1−−−・Power MO3-F
ETC3-・・・・・・・・・Resonance capacitor C!
−−−−−−−・−−−1−・−8 character correction capacitor 7
・−・−・−−−−m−−−−−−・Comparator 8
−・・−・・−・−・・・−・・Mono multi 9・−
・・・−・・−・・・・−・−・It is an or gate.

Claims (1)

【特許請求の範囲】 電源と基準電位との間に並列に接続された双方向性スイ
ッチ素子と共振コンデンサと水平偏向コイルと、 上記双方向性スイッチと上記共振コンデンサと上記水平
偏向コイルとの上記電源側における共通接続点の電圧と
基準電圧とを比較し、上記共通接続点の電圧が上記基準
電圧を越えたことを検出する比較回路と、 上記比較回路から得られる検出信号に基いて所定巾のパ
ルスを発生する回路と、 上記パルスと水平駆動パルスとが供給されて、その出力
信号により上記双方向性スイッチ素子を制御する論理和
回路とを具備して成る水平偏向回路。
[Claims] A bidirectional switch element, a resonant capacitor, and a horizontal deflection coil connected in parallel between a power source and a reference potential; a comparison circuit that compares the voltage at a common connection point on the power supply side with a reference voltage and detects that the voltage at the common connection point exceeds the reference voltage; A horizontal deflection circuit comprising: a circuit that generates a pulse; and an OR circuit that is supplied with the pulse and the horizontal drive pulse and controls the bidirectional switch element with its output signal.
JP25418786A 1986-10-25 1986-10-25 Horizontal deflecting circuit Pending JPS63108872A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP25418786A JPS63108872A (en) 1986-10-25 1986-10-25 Horizontal deflecting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25418786A JPS63108872A (en) 1986-10-25 1986-10-25 Horizontal deflecting circuit

Publications (1)

Publication Number Publication Date
JPS63108872A true JPS63108872A (en) 1988-05-13

Family

ID=17261444

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25418786A Pending JPS63108872A (en) 1986-10-25 1986-10-25 Horizontal deflecting circuit

Country Status (1)

Country Link
JP (1) JPS63108872A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005239132A (en) * 2004-01-26 2005-09-08 Toray Ind Inc Outside sheet member for vehicle

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005239132A (en) * 2004-01-26 2005-09-08 Toray Ind Inc Outside sheet member for vehicle

Similar Documents

Publication Publication Date Title
JP3617669B2 (en) Television deflection device
JP2002199243A (en) Deflection system
JP2938451B2 (en) Deflection device
US4234826A (en) Synchronous switched vertical deflection driven during both trace and retrace intervals
JPS63108872A (en) Horizontal deflecting circuit
KR100688133B1 (en) Dynamic focus voltage amplitude controller
US6118233A (en) Dynamic focus voltage disabling circuit
JP3363902B2 (en) A circuit for continuous zoom adjustment of the image width in a television receiver.
CA1283478C (en) Vertical deflection current generator
KR910009885B1 (en) Burst gate keying ans back porch clamp pulse generator
JP2560440Y2 (en) Aperture correction circuit for video system
CN1214617C (en) Grating distortion correcting circuit
US4296360A (en) Switched-mode frame-scan control circuit for a videofrequency receiver
JPH09191413A (en) Horizontal deflection circuit
US4884012A (en) Vertical deflection current generator
JP3102014B2 (en) Vertical deflection circuit
JP2000069318A (en) Image display device
JP2510284B2 (en) Horizontal deflection circuit
KR880000668Y1 (en) Blacking circuits
US6087789A (en) Hybrid bridge magnetic deflection amplifier
KR100207183B1 (en) Vertical aspect adaptive automatic brightness control circuit
JPH0799638A (en) Display method for hi-vision picture and television receiver
JPH02260766A (en) Speed modulating circuit
JPH08322057A (en) Convergence circuit
KR980007566A (en) Sub-Screen Brightness Control Circuit of Television Receiver