JPS6310878A - Image processor - Google Patents

Abstract

PURPOSE:To express a bit image loyal to a multilevel value, by negating an error generated by the binarization of the multilevel value by the next main axis and sub-axis directions. CONSTITUTION:A data conversion means is equipped with a main axis error storing means 37, a sub-axis error storing means 38, binarization means 31, 32, and 30 which compare an addition value in which the multilevel value, a main axis error, and a sub-axis error are added, with a threshold value that becomes the reference of binary coversion, and generate binary data, and error dividing means 33-36. The binary data of the bit image can be obtained by performing the binarization of the multilevel value based on the threshold value, and also, the error generated at this stage is divided into two in the main axis direction, and the sub-axis direction, then being scattered, and the error (surplus) generated in the process of division to two, is added in the main axis direction. Thus, by scattering the error generated in the process of the binary conversion in the main axis and the sub-axis directions, it is possible to suppress the degree of influence due to the error at a minimum level, and to obtain an output based on more natural binary expression.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides digitalized gradation values (brightness levels) of image data inputted by an image sensor, etc., to a pit image monitor, printer, etc. dot output,
The present invention relates to an image processing device for outputting an image as 21-ward data of non-output, lighting, and non-lighting.

[Conventional technology]

Conventional image processing methods include the dither method described in Aperture Electronics published on May 1, 1985, No. 50-64, and 75D Engineering GK from S published on April 1975.
8T, the error diffusion method described in Nos. 36 to 57 was rarely used.

[The point at which the invention attempts to solve]

The dithering method of solar electronics uses om in the input image.
(i, j) If the VC is an elemental rank iJ[Xij,
Threshold +1iI(1!ij
Since it is only possible to determine whether a cell of the display device is on or off by comparing the values, (1) the expression becomes like a pattern tile;

(2) The curved portion becomes jagged and a natural flush cannot be achieved.

(3) Gradation changes become jagged, making it impossible to express natural gradations and changes.

(4) When the expressed image is enlarged or reduced, the image is converted into continuous tiles (at the same level) using the interpolation method and the averaging method. (The averaging method is a method of compressing the upper, lower, left, and right numerical values into an appropriate averaged value.)

In addition, the error diffusion method of 75D engineering GEST from S converts the error generated at the time of conversion into two straight lines according to the gradation value Xij t-threshold to Xi+1. j, Xi+1. j+1, Xi,
Since the 4 points of j+1, Xl-1, and j+1 were weighted and diffused, (because there are many points where the υ error is diffused, the processing time until the bit image [binarization] is generated becomes very long.

(2) When diffusing errors, the calculation time for calculating weighting increases. In addition, when calculating with the number of gl, it is diffused as 7/16.1/16.5/16.3/16, so a remainder is generated and a residual error occurs, but this error can be canceled out. I don't know how.

It had the following problems.

The purpose of the present invention is to solve the above-mentioned problems, minimize the influence of errors by dispersing errors that occur in the process of binary conversion in the direction of the Mt main axis and subaxis, and create a more natural 2-value conversion process. It provides all outputs in value representation.

Furthermore, another purpose is to significantly shorten the time required for image processing since the error is only divided into two and dispersed in two directions.

Solution.

[Means to settle the issue once and for all]

As shown in the functional block diagram of FIG. 3, the image processing apparatus of the present invention includes @1 storage means (50) for storing tone value data of a pixel matrix inputted from an image input means;
a second storage flat film (40) for storing binary data of a display matrix to be output to a binary representation output means;
In an image processing apparatus comprising a data converting means for converting the gradation 11[, which is expressed by the storage means, into the binary data, the data converting means stores a main axis error occurring in the main axis direction of the matrix. an error storage means (57), a sub-axis error storage means (58) for storing a sub-axis error occurring in the sub-axis direction of the matrix, and an additional value obtained by adding the gradation value, the main axis error, and the sub@error; JbZ that generates the binary data by comparing it with a threshold value that is a standard for binary conversion;
The sub-axis error obtained by dividing the error generated in the binary conversion into two is stored in the sub-axis error storage means, and the sub-axis error and the sub-axis error obtained by dividing the error into two are stored in the sub-axis error storage means. error division means (35, 34, 35) for storing the main axis error obtained by adding the resulting remainders in the main axis error storage means;
゜56).

[Effect]

The image processing device of the present invention obtains binary data of a bit image by binarizing the gradation value directly based on a threshold, and
The error generated here is divided into two parts in the main axis direction, the sub axis direction, and the sub axis direction, and the further error that occurred at the time of the two divisions (
Add the remainder in the direction of the main axis.

〔Example〕

FIG. 1 is an overall system block diagram in an embodiment of the present invention.

Camera 5 or line scanner 4 as an image input device
The image data inputted from the digitizer 11 or the interface 12 converts the image data into analog/digital data, and stores it in the gradation value storage area of the RAM 9 via the common bus 2. Is the gradation value in RAM? Alternatively, according to a program for system startup stored in the ROM 10, the binary data is processed in 0PU1 and stored in the bit image data storage area of the RAM 9. Then, the bit image data is transmitted to 0RT5.0 as a display device. Printer controller 8 or 1d to printer 6 or facsimile 13
The images are transferred via the CRT controller 7 and output as image results according to each purpose. @ In figure 1, C
Although the PU, RAM, and ROM are written independently, some or all of these may be included in a device circuit such as a printer or a line scanner.

FIG. 2 is a memory map diagram in the RAM 9 for realizing error diffusion in the embodiment of the present invention.

A program area 20 in the RAM stores a program for carrying out the image processing of the present invention, and a nine error work area 21.
There is an error diffusion work area 23 that is used when image processing is performed in 0PU1 by an error diffusion program. This error diffusion work area 23 includes a gradation value storage area 24 that stores the gradation 11]I of the pixel obtained by A/D converting the input image data, and a gradation value storage area 24 that stores the gradation value 11]I of the pixel obtained by A/D converting the input image data. A bit image storage area 25 that stores processed bit image data, a main axis error storage area 26 that stores errors that occur in the main axis direction during the binarization process, and a secondary axis that also stores errors that occur in the fine axis direction. It is composed of an error storage area 27. Note that the program area may be provided in the ROM instead of the RAM.

FIG. 3 is a functional block diagram showing means for binarizing gradation values and error diffusion in an embodiment of the present invention.

The addition means 31 adds the main axis error and sub-axis error storage area stored in the main axis error storage area 37 to the gradation value read from the gradation value register 1'ii area 50 addressed by the area position specifying means 41. Add the secondary axis error as described in Section 38. The error addition value to which the error has been added is compared to the threshold comparison means 32.
Compare with the threshold value at . This comparison result is converted into a binary value of 1.0 by the 21 conversion means 39 and written into the bit image storage area 40 as bit image data. Next, when data indicating lighting is obtained, that is, in the case of the error addition value≧threshold value in the embodiment (error addition value>threshold value may also be acceptable), the error correction means 35 corrects the error addition value. Subtract a value. The value obtained here is the entertainment difference value when the light is turned on. In addition, when the light is not lit, the error addition value becomes the error 11μ. Then, this #A difference value is divided into two by the error separation (1/2) means 34. The error 2-divided value obtained here is written as a sub-axis error into the specified address of the area position specifying means 41 in the sub-axis error d-pixel storage area 38. Further, the value obtained by adding the error 2-divided value and the remainder 55 generated at the time of 2-division by the adding means 56 becomes the spindle section, and is written into the spindle error storage area 57. next,
The area position specifying means 41 counts and the gradation value storage area 5
0, move the addresses of the sub-axis error storage area 58 and the bit image g error storage area 40.

In this way, by sequentially changing the addresses and repeating the above operation, the gradation values stored in the gradation value storage area 30 are sequentially changed to 2.
The data is converted into a value and written into the bit image storage area 40.

The fourth row is a flowchart of the error diffusion program shown in FIG. 2 of the present invention, and according to this flowchart, the CPU performs processing equivalent to the configuration shown in FIG. 3. Here, for the sake of explanation, it is assumed that the gradation value has a level of 0 to 15, the threshold value is basically 7, and the maximum gradation value 15 is used as the correction value.

First, the axial subv4@error storage area 71 shown in FIG.
and initialize the Y-axis counter y f OK (50
). Next, the main axis error storage area 72 in the Y-axis direction and the counters x'r, o in the X-axis direction are initialized (51). Therefore, the gradation value A ''+ 7 in the gradation value storage area 75, the main axis error ay in the main axis error storage area 72, and the sub-axis error storage area 7
The sub-axis error tiX[x] of 1 is added and the variable DTK is stored (52). Comparing the variable DT with the threshold shown in the seventh factor (53), if the variable DT is less than the threshold, the bit image data Z in the bit image storage area 74 in FIG.
Set 0 to x and y (S4), and if the conversion DT is equal to or greater than the threshold value, write 1t to "pV" (55) and subtract the correction period from the variable DT (56).In this example, Although the discrimination is made based on whether it is above or below the threshold value, it may also be judged whether it exceeds the threshold value or below the threshold value.The variable D generated here
T becomes the error value, which is divided into two to give d X [x].

Write to dY (57). Furthermore, the remainder fi (DT's2) generated by dividing into two is added to the principal axis error dY (57). Therefore, (57).

The error is dispersed by (58). By repeating these flows n+1 times for xtlc and H+j times for y, the creation of bit image data is completed.

Therefore, by outputting the 730-bit image data in the bit image storage area to the ORT 5, printer 6, or facsimile 13 shown in FIG. 1, a very high-speed and accurate bit image representation can be realized.

In this embodiment, the counters in the X and Y directions are initialized to t-0 and counted up, but may be initialized to n and m and counted down. Also, the main axis and sub axis are
It doesn't matter which one you set.

Further, the correction value may be any value, and the bit image expression becomes lighter as it approaches 0, and darker as it moves away from 0. In addition, the threshold value is also changed from (minimum value + 1) to (maximum value - 1) for gradation 1 straight.
), there is no big change in the bit image representation no matter which shift is used.

[Effects of the Invention] As described above, the image processing device of the present invention cancels out errors caused by binarizing gradation values in the next main axis direction and sub-axis direction. It is possible to express a bit image that is faithful to the image. Furthermore, gradation changes in curved portions of the input image can be expressed with natural curved edges and gradation changes. Furthermore, even when the image is scaled up or down after expression, natural expressions can be scaled up or down without being converted into continuous tiles by interpolation or averaging methods that are faithful to the gradation values. 9. By enlarging and reducing the sardines using the pl# scale full-interpolation method, and then changing the gradation value to 211, natural gradation changes in scaling can be expressed.

[Brief explanation of drawings]

FIG. 1 shows a system block diagram of the present invention. FIG. 2 is a memory map diagram within the RAM of the present invention. FIG. 5 shows a block diagram showing the mFli of the present invention. FIG. 4 is a 70-chart of the error diffusion program of the present invention. FIG. 5 shows the gradation value storage area, principal axis error storage area, and
It is a table diagram of a sub-axis error MHe storage area. FIG. 6 is a table diagram of the bit image storage area of the present invention. FIG. 7 shows threshold value 2 of the present invention. Applicant Seiko Epson Co., Ltd. Agent Patent Attorney Mogami (1 other person) Figure 1 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] a first storage means for storing gradation value data of a pixel matrix inputted from the image input means; a second storage means for storing binary data of a display matrix to be output to the output means for binary expression; In an image processing apparatus comprising data conversion means for converting the gradation values stored in the storage means into the binary data, the data conversion means includes a principal axis error storage for storing principal axis errors occurring in the principal axis direction of the matrix. means, a sub-axis error storage means for storing a sub-axis error occurring in the sub-axis direction of the matrix, a sum value obtained by adding the gradation value, the main axis error and the sub-axis error, and a threshold value serving as a reference for binary conversion. 2 to generate the binary data by comparing
The error generated by the binary conversion is divided into two and stored in the sub-axis error storage means, and the main-axis error obtained by adding the sub-axis error and the remainder generated by the two-division is stored in the main-axis error storage means. An image processing apparatus comprising: error dispersion means for storing error in error storage means.