JPS6310628U - - Google Patents
Info
- Publication number
- JPS6310628U JPS6310628U JP10210886U JP10210886U JPS6310628U JP S6310628 U JPS6310628 U JP S6310628U JP 10210886 U JP10210886 U JP 10210886U JP 10210886 U JP10210886 U JP 10210886U JP S6310628 U JPS6310628 U JP S6310628U
- Authority
- JP
- Japan
- Prior art keywords
- timer
- storage means
- data
- timer control
- control device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000013500 data storage Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 1
Landscapes
- Electronic Switches (AREA)
Description
第１図は本考案によるタイマ装置の一実施例を
示すブロツク図、及び第２図は従来装置の一実施
例を示すブロツク図である。
１……バイパススイツチ、２……タイマ制御ス
イツチ、３……コントローラ、３ａ……メモリ、
３ｂ……メモリ、４……キーマトリツクス、５…
…スイツチ、１０……論理和回路、１１……イン
ジケータ。
FIG. 1 is a block diagram showing an embodiment of a timer device according to the present invention, and FIG. 2 is a block diagram showing an embodiment of a conventional device. 1... Bypass switch, 2... Timer control switch, 3... Controller, 3a... Memory,
3b...Memory, 4...Key matrix, 5...
...Switch, 10...OR circuit, 11...Indicator.
Claims (1)
イマ制御スイツチとの並列回路と、 キー入力などにより入力されるオンタイム、オ
フタイム及びタイマ制御機器選択などのデータを
記憶する記憶手段を有するコントローラとを備え
、 前記記憶手段に記憶されているデータに基づき
前記コントローラによりタイマ制御スイツチを制
御すると共に前記記憶手段からタイマ制御機器選
択データを出力するようにしたタイマ装置におい
て、 前記コントローラが前記記憶手段に記憶してい
るタイマ制御機器選択データの優先度を表わすデ
ータを記憶する優先度データ記憶手段を更に有し
、 タイマオン時前記優先度データ記憶手段中のデ
ータと前記バイパススイツチの状態との論理処理
によりタイマ制御機器選択データの出力を制御す
るようにしたことを特徴とするタイマ装置。 (2) 前記コントローラがタイマオン時にオンタ
イムになつたことを報知する報知手段を作動する
信号を出力することを特徴とする実用新案登録請
求の範囲第(1)項記載のタイマ装置。[Claims for Utility Model Registration] (1) A parallel circuit of a bypass switch and a timer control switch installed in a power supply path, and data such as on-time, off-time, and timer control device selection inputted by key input, etc. A timer device comprising: a controller having a storage means for storing; the timer control switch is controlled by the controller based on the data stored in the storage means; and timer control device selection data is output from the storage means. , further comprising a priority data storage means for storing data representing a priority of timer control device selection data stored in the storage means by the controller, and when the timer is on, the data in the priority data storage means and the bypass are stored. A timer device characterized in that the output of timer control device selection data is controlled by logical processing with the state of a switch. (2) The timer device according to claim (1), wherein the controller outputs a signal that activates a notification means to notify that the timer is on time when the timer is on.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10210886U JPH0445302Y2 (en) | 1986-07-04 | 1986-07-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10210886U JPH0445302Y2 (en) | 1986-07-04 | 1986-07-04 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6310628U true JPS6310628U (en) | 1988-01-23 |
| JPH0445302Y2 JPH0445302Y2 (en) | 1992-10-26 |
Family
ID=30973452
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10210886U Expired JPH0445302Y2 (en) | 1986-07-04 | 1986-07-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0445302Y2 (en) |
-
1986
- 1986-07-04 JP JP10210886U patent/JPH0445302Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0445302Y2 (en) | 1992-10-26 |
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